A3983
DMOS Microstepping Driver with Translator
Features and Benefits
▪
▪
▪
▪
▪
▪
Low R
DS(ON)
outputs
Automatic current decay mode detection/selection
Mixed and Slow current decay modes
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Description
The A3983 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, quarter-, and eighth-step
modes, with an output drive capacity of up to 35 V and ±2 A.
The A3983 includes a fixed off-time current regulator which
has the ability to operate in Slow or Mixed decay modes.
The translator is the key to the easy implementation of the
A3983. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A3983 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
The chopping control in the A3983 automatically selects the
current decay mode (Slow or Mixed). When a signal occurs at
the STEP input pin, the A3983 determines if that step results
in a higher or lower current in each of the motor phases. If
the change is to a higher current, then the decay mode is set to
Slow decay. If the change is to a lower current, then the current
decay is set to Mixed (set initially to a fast decay for a period
amounting to 31.25% of the fixed off-time, then to a slow
decay for the remainder of the off-time). This current decay
Continued on the next page…
Package: 24-pin TSSOP with exposed thermal pad
(suffix LP)
Not to scale
Functional Block Diagram
0.22
μF
VREG
ROSC
CP1
0.1
μF
CP2
VDD
Current
Regulator
OSC
Charge
Pump
VCP
0.1
μF
DMOS Full Bridge
REF
DAC
VBB1
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
SENSE1
Gate
Drive
R
S1
VBB2
STEP
DIR
RESET
MS1
MS2
PWM Latch
Blanking
Mixed Decay
DAC
Translator
Control
Logic
DMOS Full Bridge
OUT2A
OUT2B
ENABLE
SLEEP
SENSE2
R
S2
V
REF
26184.29D
A3983
DMOS Microstepping Driver with Translator
Description (continued)
control scheme results in reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation. Internal circuit
protection includes: thermal shutdown with hysteresis, undervoltage
Selection Guide
Part Number
A3983SLPTR-T
Package
24-pin TSSOP with exposed thermal pad
Packing
4000 pieces per 13-in. reel
lockout (UVLO), and crossover-current protection. Special power-
on sequencing is not required.
The A3983 is supplied in a low-profile (1.2 mm maximum height),
24-pin TSSOP with exposed thermal pad (suffix LP). It is lead (Pb)
free, with 100% matte tin leadframe plating.
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Output Current
Logic Input Voltage
Sense Voltage
Reference Voltage
Operating Ambient Temperature
Maximum Junction
Storage Temperature
Symbol
V
BB
I
OUT
V
IN
V
SENSE
V
REF
T
A
T
J
(max)
T
stg
Range S
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions,
do not exceed the specified current rating or a junction tem-
perature of 150°C.
Notes
Rating
35
±2
–0.3 to 7
0.5
4
–20 to 85
150
–55 to 150
Units
V
A
V
V
V
ºC
ºC
ºC
THERMAL CHARACTERISTICS
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions*
4-layer PCB, based on JEDEC standard)
Value Units
28
ºC/W
*In still air. Additional thermal information available on Allegro Web site.
5.5
5.0
Maximum Power Dissipation, P
D
(max)
Power Dissipation, P
D
(W)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
(R
θ
J
A
=
28
ºC
/W
)
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A3983
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS
1
at T
A
= 25°C, V
BB
= 35 V (unless otherwise noted)
Characteristics
Output Drivers
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
Body Diode Forward Voltage
Symbol
Test Conditions
Operating
During Sleep Mode
Operating
Source Driver, I
OUT
= –1.5 A
Sink Driver, I
OUT
= 1.5 A
Source Diode, I
F
= –1.5 A
Sink Diode, I
F
= 1.5 A
f
PWM
< 50 kHz
Operating, outputs disabled
Sleep Mode
f
PWM
< 50 kHz
Outputs off
Sleep Mode
Min.
8
0
3.0
–
–
–
–
–
–
–
–
–
–
V
DD
0.7
V
IN
= V
DD
0.7
–
–20
–20
–
150
0.7
20
23
0
–3
–
–
–
100
–
–
2.35
0.05
Typ.
2
–
–
–
0.350
0.300
–
–
–
–
–
–
–
–
–
–
<1.0
<1.0
100
300
1
30
30
–
0
–
–
–
475
165
15
2.7
0.10
Max.
35
35
5.5
0.450
0.370
1.2
1.2
4
2
10
8
5
10
–
V
DD
0.3
20
20
–
500
1.3
40
37
4
3
±15
±5
±5
800
–
–
3
–
Units
V
V
V
Ω
Ω
V
V
mA
mA
μA
mA
mA
μA
V
V
μA
μA
kΩ
mV
μs
μs
μs
V
μA
%
%
%
ns
°C
°C
V
V
V
BB
V
DD
R
DSON
V
F
I
BB
Motor Supply Current
Logic Supply Current
Control Logic
Logic Input Voltage
Logic Input Current
Microstep Select 2
Input Hysteresis
Blank Time
Fixed Off-Time
Reference Input Voltage Range
Reference Input Current
Current Trip-Level Error
3
Crossover Dead Time
Protection
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
I
DD
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
MS2
V
HYS(IN)
t
BLANK
t
OFF
V
REF
I
REF
err
I
V
IN
= V
DD
0.3
OSC > 3 V
R
OSC
= 25 kΩ
V
REF
= 2 V,
%I
TripMAX
=
38.27%
V
REF
= 2 V,
%I
TripMAX
= 70.71%
V
REF
= 2 V,
%I
TripMAX
= 100.00%
t
DT
T
J
T
JHYS
UV
LO
UV
HYS
V
DD
rising
1
Negative current is defined as coming out of (sourcing from) the specified device pin.
2
Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
3
err
individual units, within the specified maximum and minimum limits.
I
= (I
Trip
– I
Prog
)
⁄
I
Prog
, where I
Prog
= %I
TripMAX
I
TripMAX
.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A3983
DMOS Microstepping Driver with Translator
t
A
t
B
STEP
t
C
MS1, MS2,
RESET, or DIR
t
D
Time Duration
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
Setup time, input change to STEP
Hold time, input change to STEP
Figure 1. Logic Interface Timing Diagram
Symbol
t
A
t
B
t
C
t
D
Typ.
1
1
200
200
Unit
μs
μs
ns
ns
Table 1. Microstep Resolution Truth Table
MS1
L
H
L
H
MS2
L
L
H
H
Microstep Resolution
Full Step
Half Step
Quarter Step
Eighth Step
Excitation Mode
2 Phase
1-2 Phase
W1-2 Phase
2W1-2 Phase
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A3983
DMOS Microstepping Driver with Translator
Functional Description
Device Operation.
The A3983 is a complete microstep-
ping motor driver with a built-in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, quarter-, and sixteenth-step
modes. The currents in each of the two output full-bridges
and all of the N-channel DMOS FETs are regulated with
fixed off-time PMW (pulse width modulated) control cir-
cuitry. At each step, the current for each full-bridge is set by
the value of its external current-sense resistor (R
S1
or R
S2
), a
reference voltage (V
REF
), and the output voltage of its DAC
(which in turn is controlled by the output of the translator).
At power-on or reset, the translator sets the DACs and the
phase current polarity to the initial Home state (shown in fig-
ures 2 through 5), and the current regulator to Mixed Decay
Mode for both phases. When a step command signal occurs
on the STEP input, the translator automatically sequences the
DACs to the next level and current polarity. (See table 2 for
the current-level sequence.) The microstep resolution is set
by the combined effect of inputs MS1 and MS2, as shown in
table 1.
When stepping, if the new output levels of the DACs are
lower than their previous output levels, then the decay mode
for the active full-bridge is set to Mixed. If the new output
levels of the DACs are higher than or equal to their previous
levels, then the decay mode for the active full-bridge is set
to Slow. This automatic current decay selection improves
microstepping performance by reducing the distortion of
the current waveform that results from the back EMF of the
motor.
Microstep Select
(MS1 and MS2).
Selects the micro-
stepping format, as shown in table 1. MS2 has a 100 kΩ pull-
down resistance. Any changes made to these inputs do not take
effect until the next STEP rising edge.
Direction Input
(DIR).
This determines the direction of
rotation of the motor. When low, the direction will be clock-
wise and when high, counterclockwise. Changes to this input
do not take effect until the next STEP rising edge.
Internal PWM Current Control.
Each full-bridge is
controlled by a fixed off-time PWM current control circuit
that limits the load current to a desired value, I
TRIP
. Ini-
tially, a diagonal pair of source and sink DMOS outputs are
enabled and current flows through the motor winding and
the current sense resistor, R
Sx
. When the voltage across R
Sx
equals the DAC output voltage, the current sense compara-
tor resets the PWM latch. The latch then turns off either the
source DMOS FETs (when in Slow Decay Mode) or the sink
and source DMOS FETs (when in Mixed Decay Mode).
The maximum value of current limiting is set by the selec-
tion of R
Sx
and the voltage at the VREF pin. The transcon-
ductance function is approximated by the maximum value of
current limiting, I
TripMAX
(A), which is set by
I
TripMAX
= V
REF
/ ( 8
R
S
)
where R
S
is the resistance of the sense resistor (Ω) and V
REF
is the input voltage on the REF pin (V).
The DAC output reduces the V
REF
output to the current
sense comparator in precise steps, such that
I
trip
= (%I
TripMAX
/ 100)
×
I
TripMAX
(See table 2 for %I
TripMAX
at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1
and SENSE2 pins is not exceeded.
RESET Input (RESET).
The RESET input sets the
translator to a predefined Home state (shown in figures 2
through 5), and turns off all of the DMOS outputs. All STEP
inputs are ignored until the RESET input is set to high.
Step Input
(STEP)
.
A low-to-high transition on the STEP
input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
the direction of current flow in each winding. The size of
the increment is determined by the combined state of inputs
MS1 and MS2.
Fixed Off-Time.
The internal PWM current control cir-
cuitry uses a one-shot circuit to control the duration of time
that the DMOS FETs remain off. The one shot off-time, t
OFF
,
is determined by the selection of an external resistor con-
nected from the ROSC timing pin to ground. If the ROSC
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
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