2M x 8 SRAM MODULE
SYS82000RKXC - 70/85/10/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.2 : January 1999
Features
•
•
Access Times of 70/85/100/120 ns.
Low Power Disapation:
Operating
600 mW (Max.)
Standby-L Version
1.1 mW (Max.)
5 Volt Supply ± 10%.
Completely Static Operation.
Low Voltage V
CC
Data Retention.
On-board Decoding & Decoupling Capacitors.
38 Pin Single-In-Line package (SIP).
Upgrade path to SYS84000RKXC (32Mbits).
Description
The SYS82000RKXC is a plastic 16Mbit Static
RAM Module housed in a standard 38 pin Single In-
Line package organised as 2M x 8 with access
times of 70, 85,100, or 120 ns.
The module is constructed using four 512Kx8
SRAMs in TSOPII packages mounted onto an FR4
epoxy substrate. This offers an extremely high
PCB packing density.
The device is offered in standard and low power
versions, with the -L module having a low voltage
data retention mode for battery backed applications.
•
•
•
•
•
•
Block Diagram
Pin Definition
NC
A20
Vcc
WE
D2
D3
D0
A1
A2
A3
A4
GND
D5
A10
A11
A5
A13
A14
A19
CS
A15
A16
A12
A18
A6
D1
GND
A0
A7
A8
A9
D7
D4
D6
A17
Vcc
OE
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
D0 - D7
A0 - A18
OE
WE
512K x 8
SRAM
CS
512K x 8
SRAM
CS
512K x 8
SRAM
CS
512K x 8
SRAM
CS
A19
A20
CS
DECODER
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 ~ A20
D0 ~ D7
CS
WE
OE
NC
V
CC
GND
Pin 38 is A21 on the
SYS84000RKXC upgrade module.
Package Details
Plastic 38 pin Single-In-Line (SIP)
ISSUE 1.2 : January 1999
SYS82000RKXC - 70/85/10/12
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Notes :
Symbol
V
T
P
T
T
STG
min
-0.3
-
-55
typ
-
-
-
max
+7
4.0
+125
unit
V
W
o
C
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at those or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
(2) V
T
can be -3.0 V pulse of less than 30 ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
min
4.5
2.2
-0.3
0
-40
typ
5.0
-
-
-
-
max
5.5
Vcc+0.3
0.8
70
85
unit
V
V
V
o
C
o
C (I)
DC Electrical Characteristics
(V
CC
=5V±10%)
T
A
0 to 70
O
C
Parameter
I/P Leakage Current
Output Leakage Current
Operating Supply Current
Standby Supply Current TTL levels
-L Version
Output Low Voltage
Output High Voltage
Symbol Test Condition
I
LI
I
LO
I
CC
I
SB1
I
SB2
V
OL
V
OH
min
typ
-
-
-
-
-
-
-
max Unit
4
4
109
12
200
0.4
-
µA
µA
mA
mA
µA
V
V
V
IN
= GND to V
CC
-4
CS = V
IH
, V
I/O
= GND to V
CC
-4
CS = V
IL
, min cycle, Duty = 100%
-
CS = V
IH
-
CS = V
CC
-0.2V, 0.2 > V
IN
> V
CC
-0.2V -
I
OL
= 2.1mA
-
I
OH
= -1.0mA
2.4
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Note: Capacitance calculated, not measured.
Parameter
Input Capacitance (CS,A19,A20)
Input Capacitance (A0-18,OE,WE)
I/O Capacitance
Symbol
C
IN1
C
IN2
C
I/O
Test Condition
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
typ
-
-
-
max
8
32
10
Unit
pF
pF
pF
2
SYS82000RKXC - 70/85/10/12
ISSUE 1.2 January 1999
Operation Truth Table
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
DATA PINS
High Impedance
Data Out
Data In
High Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
I
CC
I
CC
I
CC
MODE
Standby
Read
Write
Output Disabled
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
AC Test Conditions
*
Input pulse levels: 0 V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
= 5V± 10%
I/O Pin
Output Load
645
Ω
1.76V
100pF
Low V
cc
Data Retention Characteristics - L Version Only (T
OP
= 0°C to 70°C)
Parameter
V
CC
for Data Retention
Symbol Test Condition
V
DR
CS>V
CC
-0.2V
-L Part
min typ max
2.0
-
Unit
V
µA
ns
ms
-
-
-
-
-
400
-
-
0.2V>V
in
>V
cc
-0.2
Data Retention Current
I
CCDR
Chip Deselect to Data Ret. Time t
CDR
Operation Recovery Time
t
R
V
CC
=3.0V,CS=V
CC
-0.2V,0.2V>V
in
>V
cc
-0.2
See Retention Waveform
See Retention Waveform
0
5
3
ISSUE 1.2 : January 1999
SYS82000RKXC - 70/85/10/12
AC OPERATING CONDITIONS
Read Cycle
-70
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
70
-
-
-
10
10
5
0
0
max
-
70
70
40
-
-
-
30
30
-85
min
85
-
-
-
10
10
5
0
0
max
-
85
85
45
-
-
-
30
30
-10
min
100
-
-
-
10
10
5
0
0
max
-
100
100
50
-
-
-
35
35
-12
min
120
-
-
-
10
10
5
0
0
max
-
120
120
55
-
-
-
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-70
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
70
60
0
60
55
5
0
30
0
5
max
-
-
-
-
-
-
25
-
-
-
-85
min
85
75
0
75
65
5
0
35
0
5
max
-
-
-
-
-
-
30
-
-
-
-10
min
100
80
0
80
70
5
0
40
0
5
max
-
-
-
-
-
-
35
-
-
-
-12
min
120
100
0
100
80
5
0
45
0
5
max
-
-
-
-
-
-
40
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
SYS82000RKXC - 70/85/10/12
ISSUE 1.2 January 1999
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are
not referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
OW
(8)
Dout
High-Z
t
DH
Din
Data Valid
5
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