• 1N6639US THRU 1N6641US AVAILABLE IN
JAN, JANTX, JANTXV
AND
JANS
PER MIL-PRF-19500/609
• SWITCHING DIODES
• NON-CAVITY GLASS PACKAGE
• METALLURGICALLY BONDED
1N6639US
1N6640US
1N6641US
MAXIMUM RATINGS
Operating Temperature: -65°C to +175°C
Storage Temperature: -65°C to +175°C
Operating Current: 300 mA
Derating: 4.6 mA/°C Above TEC = + 110°C
Surge Current: I
FSM
= 2.5A, Pw = 8.3ms
ELECTRICAL CHARACTERISTICS
@ 25°C, unless otherwise specified.
V BRR
@ 10 µA
V RWM
I R1
I R2
@ TA = +25
°C
@ TA = +150
°C
VR =
VR =
V RWM
V RWM
nA dc
100
100
100
µA dc
100
100
100
T FR
IF
= 200 mA
T RR
I R = 10 mA
I F = 10 mA
RL = 100
Ω
ns
4.0
4.0
5.0
CT
VR = 0
DIM
D
F
G
S
MILLIMETERS
MIN
MAX
1.78
2.16
0.48
0.71
4.19
4.95
0.08MIN.
INCHES
MIN MAX
0.070 0.085
0.019 0.028
0.165 0.195
0.003MIN.
TYPES
FIGURE 1
pF
2.5
2.5
3.0
V(pk)
1N6639US
1N6640US
1N6641US
100
75
75
V(pk)
75
50
50
ns
10
10
10
DESIGN DATA
CASE:
D-5D, Hermetically sealed glass
case, per MIL-PRF- 19500/609
FORWARD VOLTAGE:
VF
TYPES
MIN
1N6639US
–
0.54
1N6640US
0.76
0.82
0.87
1N6641US
–
VdC
MAX
1.20
0.62
0.86
0.92
1.00
1.10
@
IF
mA
(PULSED)
500
1
50
100
200
200
LEAD FINISH:
Tin / Lead
THERMAL RESISTANCE: (R
OJEC):
50 ˚C/W maximum at L = 0
THERMAL IMPEDANCE: (Z
OJX): 25
˚C/W maximum
POLARITY:
Cathode end is banded
MOUNTING SURFACE SELECTION:
The Axial Coefficient of Expansion
(COE) of this device is approximately
+ 4PPM / °C. The COE of the Mounting
Surface System should be selected to
provide a suitable match with this
device.
22 COREY STREET, MELROSE, MASSACHUSETTS 02176
PHONE (781) 665-1071
FAX (781) 665-7379
WEBSITE: http://www.cdi-diodes.com
E-mail: mail@cdi-diodes.com
IN6639US
1000
thru
IN6641US
100
IF - Forward Current - (mA)
10
15
0ºC
100
ºC
0.1
.2
.3
.4
.5
.6
.7
.8
.9
VF - Forward Voltage (V)
FIGURE 2
Typical Forward Current
vs Forward Voltage
1.0
1.1
1.2
1000
100
150ºC
IR - Reverse Current - (µA)
10
C
100º
1
0.1
25ºC
.01
-65ºC
-65ºC
1
25º
C
NOTE :
All temperatures shown on graphs are
junction temperatures
.001
20 40 60 80 100 120 140
Percent of Reverse Working Voltage (%)
FIGURE 3
Typical Reverse Current
vs Reverse Voltage
FPGA/CPLD
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