HS-3282
REFERENCE AN400
March 1997
CMOS ARINC Bus Interface Circuit
Description
The HS-3282 is a high performance CMOS bus interface
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
serial data protocols. This device is intended to be used with
the HS-3182, a monolithic Dl bipolar differential line driver
designed to meet the specifications of ARINC 429. The
ARINC 429 bus interface circuit consists of two (2) receivers
and a transmitter operating independently as shown in
Figure 1. The two receivers operate at a frequency that is ten
(10) times the receiver data rate, which can be the same or
different from the transmitter data rate. Although the two
receivers operate at the same frequency, they are
functionally independent and each receives serial data asyn-
chronously. The transmitter section of the ARINC bus
interface circuit consists mainly of a First-In First-Out (FIFO)
memory and timing circuit. The FIFO memory is used to hold
up to eight (8) ARINC data words for transmission serially.
The timing circuit is used to correctly separate each ARINC
word as required by ARINC Specification 429. Even though
ARINC Specification 429 specifies a 32-bit word, including
parity, the HS-3282 can be programmed to also operate with
a word length of 25 bits. The incoming receiver data word
parity is checked, and a parity status is stored in the receiver
latch and output on Pin BD08 during the 1st word. [A logic
“0” indicates that an odd number of logic “1” s were received
and stored; a logic “1” indicates that an even number of logic
“1”s were received and stored]. In the transmitter the parity
generator will generate either odd or even parity depending
upon the status of PARCK control signal. A logic “0” on BD12
will cause odd parity to be used in the output data stream.
Versatility is provided in both the transmitter and receiver by
the external clock input which allows the bus interface circuit
to operate at data rates from 0 to 100 kilobits. The external
clock must be ten (10) times the data rate to insure no data
ambiguity.
The ARINC bus interface circuit is fully guaranteed to
support the data rates of ARINC specification 429 over both
the voltage (±5%) and full military temperature range. It
interfaces with UL, CMOS or NMOS support circuitry, and
uses the standard 5-volt V
CC
supply.
Features
• ARlNC Specification 429 Compatible
• Data Rates of 100 Kilobits or 12.5 Kilobits
• Separate Receiver and Transmitter Section
• Dual and Independent Receivers, Connecting Directly
to ARINC Bus
• Serial to Parallel Receiver Data Conversion
• Parallel to Serial Transmitter Data Conversion
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
• Generate Parity of Transmitter Data
• Automatic Word Gap Timer
• Single 5V Supply
• Low Power Dissipation
• Full Military Temperature Range
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
-40
o
C to +85
o
C
-55
o
C to +125
o
C
SMD#
TEMP. RANGE
-55
o
C to +125
o
C
PART NUMBER
HS1-3282-8
5962-8688001QA
HS4-3282-9+
HS4-3282-8
5962-8688001XA
PKG.
NO.
F40.6
F40.6
J44.A
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2964.2
5-183
HS-3282
Pinouts
HS-3282 (CERDIP)
TOP VIEW
V
DD
429DI1(A)
429DI1(B)
429DI2(A)
429DI2(B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 NC
39 MR
38 TX CLK
37 CLK
36 NC
35 NC
34 CWSTR
33 ENTX
32 429D0
31 429D0
30 TX/R
29 PL2
28 PL1
27 BD00
26 BD01
25 BD02
24 BD03
23 BD04
22 BD05
21 GND
HS-3282 (CLCC)
TOP VIEW
429DI1(B)
429DI2(B)
429DI2(A)
429DI1(A)
TXCLK
NC
CLK
V
DD
NC
MR
6
NC 7
D/R1 8
D/R2 9
SEL 10
EN1 11
EN2 12
BD15 13
BD14 14
BD13 15
BD12 16
BD11 17
5
4
3
2
1 44 43 42 41 40
39 NC
38 NC
37 CWSTR
36 ENTX
35 429D0
34 429D0
33 TX/R
32 PL2
31 PL1
30 BD00
29 BD01
18 19 20 21 22 23 24 25 26 27 28
NC
BD10
BD09
BD08
BD07
BD06
BD05
BD04
BD03
BD02
GND
5-184
NC
HS-3282
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
V
CC
429 DI1 (A)
429 DI1 (B)
429 Dl2 (A)
429 DI2 (B)
D/R1
D/R2
SEL
EN1
EN2
BD15
SECTION
Recs/Trans
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Recs/Trans
Supply pin 5 volts
±5%.
ARlNC 429 data input to Receiver 1.
ARlNC 429 data input to Receiver 1.
ARINC 429 data input to Receiver 2.
ARINC 429 data input to Receiver 2.
Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched.
Device ready flag output from Receiver 2 indicating a valid data word is ready to be fetched.
Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2.
Input signal to enable data from Receiver 1 onto the data bus.
Input signal to enable data from Receiver 2 onto the data bus.
Bi-directional data bus for fetching data from either of the Receivers, or for loading data into
the Transmitter memory or control word register. See Control Word Table for description of
Control Word bits.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
See Pin 11.
Circuit Ground.
See Pin 11.
See Pin 11. Control Word function not applicable.
See Pin 11. Control Word function not applicable.
See Pin 11. Control Word function not applicable.
See Pin 11. Control Word function not applicable.
See Pin 11. Control Word function not applicable.
Parallel load input signal loading the first 16-bit word into the Transmitter memory.
Parallel load input signal loading the first 16-bit word into the Transmitter memory and initiates
data transfer into the memory stack.
Transmitter flag output to indicate the memory is empty.
DESCRIPTION
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
PL1
PL2
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Recs/Trans
Transmitter
Transmitter
30
TX/R
Transmitter
5-185
HS-3282
Pin Description
PIN
31
32
33
34
SYMBOL
429D0
429D0
ENTX
CWSTR
(Continued)
SECTION
Transmitter
Transmitter
Transmitter
Recs/Trans
Data output from Transmitter
Data output from Transmitter.
Transmitter Enable input signal to initiate data transmission from FIFO memory.
Control word input strobe signal to latch the control word from the databus into the control
word register.
No connection. Must be left open.
No connection. Must be left open or tied low but never tied high.
External clock input. May be either ten (10) or eighty (80) times the data rate. If using both
ARINC data rates it must be ten (10) times the highest data rate, (typically 1MHz).
Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate.
Master Reset. Active low pulse used to reset FIFO, bit counters, gap timer, word count signal,
TX/R and various other flags and controls. Master reset does not reset the control word
register. Usually only used on Power-Up or System Reset.
No Connection.
DESCRIPTION
35
36
37
-
-
CLK
-
-
Recs/Trans
38
39
TXCLK
MR
Transmitter
Recs/Trans
40
-
-
Pinout
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC NC
NC
5-186
HS-3282
Operational Description
The HS-3282 is designed to support ARINC Specification
429 and other serial data protocols that use a similar format
by collecting the receiving, transmitting, synchronizing,
timing and parity functions on a single, low power LSl circuit.
It goes beyond the ARlNC requirements by providing for
either odd or even parity, and giving the user a choice of
either 25 or 32-bit word lengths. The receiver and transmitter
sections operate independently of each other. The serial-to-
parallel conversion required of the receiver and the parallel-
to-serial conversion requirements of the transmitter have
been incorporated into the bus interface circuit.
Provisions have been made through the external clock input
to provide data rate flexibility. This requires an external clock
that is 10 times the data rate.
To obtain the flexibility discussed above, a number of
external control signals are required, To reduce the pin count
requirements, an internal control word register is used. The
control word is latched from the data bus into the register by
the Control Word Strobe (CWSTR) signal going to a logic
“1”. Eleven (11) control functions are used, and along with
the Bus Data (BD) line are listed below:
Control Word
PIN NAME
BD05
SYMBOL
SLFTST
FUNCTION
Connects the self test signal from the transmitter directly to the receiver shift registers, bypassing the input
receivers. Receiver 1 receives Data True and Receiver 2 receives Data Not. Note that the transmitter output
remains active. (Logic “0” on SLFTST Enables Self Test).
Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder).
If SDENB1 = “1” then this bit is compared with ARlNC Data Bit #9. If Y1 also matches (see Y1), the word will be
accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
If SDENBI = “1” then this bit is compared with ARINC Data Bit #10. If X1 also matches (see X1), the word will
be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder).
If SDENB2 = “1” then this bit is compared with ARlNC Data Bit #9. If Y2 also matches (see Y2), the word will be
accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
If SDENB2 = “1” then this bit is compared with ARINC Data Bit #10. If X2 also matches (see X2), the word will
be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
Signal used to invert the transmitter parity bit for test of parity circuits. Logic “0” selects normal odd parity. Logic
“I” selects even parity.
Selects high or low Transmitter data rate. If TXSEL = “0” then transmitter data rate is equal to the clock rate
divided by ten (10). If TXSEL = “1” then transmitter data rate is equal to the clock rate divided by eighty (80).
Selects high or low Receiver data rate. If RCVSEL = “0” then the received data rate should be equal to the clock
rate divided by ten (10), if RCVSEL = “1 “then the received data rate should be equal to the clock rate divided
by eighty (80).
Selects word length. If WLSEL = “0” a 32-bit word format will be selected. If WLSEL = “1” a 25-Bit word format
will be selected.
BD06
BD07
BD08
BD09
BD10
BD11
BD12
BD13
BD14
SDENB1
X1
Y1
SDENB2
X2
Y2
PARCK
TXSEL
RCVSEL
BD15
WLSEL
ARlNC 429 DATA FORMAT as input to the Receiver and out-
put from the Transmitter is as follows:
TABLE 1. ARINC 429 32-BIT DATA FORMAT
ARINC BIT #
1-8
9 - 10
11
12 - 27
28
29
30, 31
32
FUNCTION
Label
SDl or Data
LSB
Data
MSB
Sign
SSM
Parity Status
This format is shuffled when seen on the sixteen bidirec-
tional input/outputs. The format shown below is used from
the receivers and input to the transmitter:
TABLE 2A. WORD 1 FORMAT
BI-DIRECTIONAL
BIT #
15, 14
13
12, 11
10, 9
8
7 - 00
FUNCTION
Data
LSB
SDl or Data
SSM Status
Parity Status
Label
ARINC BlT #
13, 12
11
10, 9
31, 30
32
1-8
5-187
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