L67130/L67140
1 K
×
8 CMOS Dual Port RAM 3.3 Volt
Introduction
The L67130/67140 are very low power CMOS dual port
static RAMs organized as 1024
×
8. They are designed to
be used as a stand-alone 8 bits dual port RAM or as a
combination MASTER/SLAVE dual port for 16 bits or
more width systems. The MHS MASTER/SLAVE dual
port approach in memory system applications results in
full speed, error free operation without the need for
additional discrete logic.
Master and slave devices provide two independent ports
with separate control, address and I/O pins that permit
independent, asynchronous access for reads and writes to
any location in the memory. An automatic power down
feature controlled by CS permits the onchip circuitry of
each port in order to enter a very low stand by power
mode.
Using an array of eight transistors (8T) memory cell and
fabricated with the state of the art 1.0
µm
lithography
named SCMOS, the M67130/140 combine an extremely
low standby supply current (typ = 1.0
µA)
with a fast
access time at 45 ns over the full temperature range. All
versions offer battery backup data retention capability
with a typical power consumption at less than 5
µW.
For military/space applications that demand superior
levels of performance and reliability the L67130/67140
is processed according to the methods of the latest
revision of the MIL STD 883 (class B or S) and/or ESA
SCC 9000.
Features
D
Single 3.3 V
±
0.3 volt power supply
D
Fast access time
45 ns(*) to 70 ns
D
67130L/67140L low power
67130V/67140V very low power
D
Expandable data bus to 16 bits or more using master/slave
devices when using more than one device.
(*) Preliminary
D
D
D
D
D
D
On chip arbitration logic
BUSY output flag on master
BUSY input flag on slave
INT flag for port to port communication
Fully asynchronous operation from either port
Battery backup operation : 2 V data retention
MATRA MHS
Rev. D (19 Fev. 97)
1
L67130/L67140
Interface
Pin Configuration
48 PIN DIL (top view), ceramic,
plastic 600 mils
52 PIN PLCC (top view)
48 PIN PLCC (top view)
64 PIN VQFP
(top view)
Block Diagram
Notes :
1. L 67130 (MASTER) : BUSY is open drain output and requires pullup resistor
L 67140 (SLAVE) : BUSY in input
2. Open drain output requires pull-up resistor.
2
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
Pin Names
LEFT PORT
CS
L
R/W
L
OE
L
A
0L – 9L
I/O
0L – 7L
BUSY
L
INT
L
VCC
GND
RIGHT PORT
CS
R
R/W
R
OE
R
A
0R – 9R
I/O
0R – 7R
BUSY
R
INT
R
NAMES
Chip select
Write Enable
Output Enable
Address
Data Input/Output
Busy Flag
Interrupt Flag
Power
Ground
Functional Description
The L 67130/L 67140 has two ports with separate control,
address and I/0 pins that permit independent read/write
access to any memory location. These devices have an
automatic power-down feature controlled by CS. CS
controls on-chip power-down circuitry which causes the
port concerned to go into stand-by mode when not
selected (CS high). When a port is selected access to the
full memory array is permitted. Each port has its own
Output Enable control (OE). In read mode, the port’s OE
turns the Output drivers on when set LOW.
Non-conflicting
READ/WRITE
conditions
are
illustrated in table 1.
Arbitration Logic
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns and
determine which port has access. In all cases, an active
BUSY flag will be set for the inhibited port.
The BUSY flags are required when both ports attempt to
access the same location simultaneously.Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the
inhibited port. BUSY is set at speeds that allow the
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
A conflict will occur when both left and right ports are
active and the two addresses coincide. The on-chip
arbitration determines access in these circumstances.
Two modes of arbitration are provided : (1) if the
addresses match and are valid before CS on-chip control
logic arbitrates between CS
L
and CS
R
for access ; or (2)
if the CSs are low before an address match, on-chip
control logic arbitrates between the left and right
addresses for access (refer to table 2). The inhibited port’s
BUSY flag is set and will reset when the port granted
access completes its operation in both arbitration modes.
Interrupt Logic
The interrupt flag (INT) allows communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
is assigned to each port. The left port interrupt flag (INT
L
)
is set when the right port writes to memory location 3FE
(HEX). The left port clears the interrupt by reading
address location 3FE. Similarly, the right port interrupt
flag (INT
R
) is set when the left port writes to memory
location 3FF (hex), and the right port must read memory
location 3FF in order to clear the interrupt flag (INT
R
).
The 8 bit message at 3FE or 3FF is user-defined. If the
interrupt function is not used, address locations 3FE and
3FF are not reserved for mail boxes but become part of the
RAM. See table 3 for the interrupt function.
MATRA MHS
Rev. D (19 Fev. 97)
3
L67130/L67140
Data Bus Width Expansion
Master/Slave Description
Expanding the data bus width to 16 or more bits in a
dual-port RAM system means that several chips may be
active simultaneously. If every chip has a hardware
arbitrator, and the addresses for each chip arrive at the
same time one chip may activate its L BUSY signal while
another activates its R BUSY signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
To overcome this “Busy Lock-Out” problem, MHS has
developed a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to
the MASTER with no external components, giving a
speed advantage over other systems.
When dual-port RAMs are expanded in width, the
SLAVE RAMs must be prevented from writing until the
BUSY input has been settled. Otherwise, the SLAVE chip
may begin a write cycle during a conflict situation. On the
opposite, the write pulse must extend a hold time beyond
BUSY to ensure that a write cycle occurs once the conflict
is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the
same time.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
Truth Table
Table 1 : Non Contention Read/Write Control
(4)
LEFT OR RIGHT PORT
(1)
FUNCTION
R/W
X
L
H
H
Notes :
CS
H
L
L
L
OE
X
X
L
H
D0–7
Z
DATA
IN
DATA
OUT
Z
Port Disabled and in Power Down Mode. ICCSB or ICCSB1
Data on Port Written into memory
(2)
Data in Memory Output on Port
(3)
High Impedance Outputs
1. A
0L
– A
10L
≠
A
0R
– A
10R
.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
WDD
and t
DDD
timing.
4. H = HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE.
4
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
Table 2 : Arbitration
(5)
LEFT PORT
CS
L
H
L
H
L
RIGHT PORT
CS
R
H
H
L
L
FLAGS
FUNCTION
BUSY
L
H
H
H
H
A
0L
– A
9L
X
Any
X
≠
A
0R
– A
9R
A
0L
– A
9R
X
X
Any
≠
A
0L
– A
9L
BUSY
R
H
H
H
H
No Contention
No Contention
No Contention
No Contention
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
L
L
L
LV5R
RV5L
Same
Same
L
L
L
L
LV5R
RV5L
Same
Same
H
L
H
L
L
H
L
H
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
RL5L
LW5R
LW5R
Notes :
= A
0R
– A
9R
= A
0R
– A
9R
= A
0R –
A
9R
= A
0R
– A
9R
LL5R
RL5L
LW5R
LW5R
= A
0L
– A
9L
= A
0L –
A
9L
= A
0L
– A
9L
= A
0L
– A
9L
H
L
H
L
L
H
L
H
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
5. INT Flags Don’t Care.
6. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid
≥
5 ns before right address.
RV5L = Right address Valid
≥
5 ns before left address.
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW
≥
5 ns before Right CS.
RL5L = Right CS = LOW
≥
5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
Table 3 : Interrupt Flag
(7, 10)
LEFT PORT
R/W
L
L
X
X
X
Notes :
7.
8.
9.
10.
RIGHT PORT
FUNCTION
INT
L
X
X
L
(9)
H
(8)
CS
L
L
X
X
L
OE
L
X
X
X
L
A
OL
–A
9L
3FF
X
X
3FE
R/W
R
X
X
L
X
CS
R
X
L
L
X
OE
R
X
L
X
X
A
OR
–A
9R
X
3FF
3FE
X
INT
R
L
(8)
H
(9)
X
X
Set Right INT
R
Flag
Reset Right INT
R
Flag
Set Left INT
L
Flag
Reset Left INT
L
Flag
Assumes BUSY
L
= BUSY
R
= H.
If BUSY
L
= L, then NC.
If BUSY
R
= L, then NC.
H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.
MATRA MHS
Rev. D (19 Fev. 97)
5
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