Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator
with Sleep Mode, External Synchronization, and POK Output
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
[1]
Characteristic
VIN, SLEEP, SS Pin Voltage
SW Pin Voltage
BOOT Pin Voltage
All Other Pin Voltages
Maximum Junction Temperature
Storage Temperature
[1]
Symbol
Notes
Continuous (minimum limit is a function of temperature)
t < 50 ns
Continuous
BOOT OV Fault Condition
Rating
–0.3 to 40
–0.3 to V
IN
+ 0.3
–1.0 to V
IN
+ 0.3
V
SW
– 0.3 to V
SW
+ 5.5
V
SW
– 0.3 to V
SW
+ 7.0
–0.3 to 5.5
150
–55 to 150
Unit
V
V
V
V
V
V
°C
°C
V
SW
V
BOOT
T
J(max)
T
stg
Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratingsare stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute
Maximum-rated conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS:
May require derating at maximum conditions, see application information
Characteristic
Package Thermal Resistance
[2]
Additional
Symbol
R
qJA
Test Conditions
[2]
On 4-layer PCB based on JEDEC standard
Value
37
Unit
°C/W
thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
ARG81801
Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator
with Sleep Mode, External Synchronization, and POK Output
VIN
VIN
TEST
BIAS
BOOT REG
.
BOOT
OFF
OC
250 mA
TEST
LDO
OFF
3.05 V
3.8 V
3.4 V
BG
–
+
UVLO
5.0 V
VREG
DELAY
–
1.205 V
POR
2 V,
4.1 V
Q
EN
BOOT
REG
Digital
SLEEP\
103 µs↓
2.90 V
+
400 mV
BOOT
OFF
BOOT
FAULT
+
–
BOOT
f
SYNC
> 1.2 × f
OSC
FSET
f
OSC
sleep
PWM
f
OSC
f
OSC
/2
f
OSC
/4
FB < 0.2 V
FB < 0.4 V
blankOn
minOff
S
R
Q
Q
+
S
E
I
SENSE
G
CSA
110 m
Q
maxDuty
VREG
10
SYNC
R
SYNC
Current
Comp
f
SW
SW
SW
swLoDet
DIODEOK
BOOT < 4.1V
I
FB
FB
800 mV
ERROR
AMP
sleep
PWM
CLAMP
OCL
ssDischarge
COMP
400 mV
FB < 740 mV
FB > 880 mV
OCL
swLoDet
DIODEOK
BOOT FAULT
UVLO
POR
TSD
FB > 880 mV
FB < 740 mV
–
sleep
PWM
sleep
PWM
maxDuty
IDLE-STOP
compFalling RECOVERY
CONTROL
Functional Block Diagram
+
5 µA
20 µA
HICCUP
SS
1k
2k
FAULT
LOGIC
(See Fault
Table)
sleep
PWM
HIC SET
HIC RST
HICCUP
LOGIC
PULL DOWN
BOOT OFF
POK
DELAY
26 s↓
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
ARG81801
Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator
with Sleep Mode, External Synchronization, and POK Output
PINOUT DIAGRAM AND TERMINAL LIST
19 BOOT
18 SW
17 SW
PAD
16 GND
15 VREG
14 TEST
13 FB
NC 10
COMP 12
NC 11
24 NC
23 NC
22 NC
NC
9
21 NC
20 NC
VIN
VIN
SS
SLEEP
GND
SYNC
1
2
3
4
5
6
7
Package ES, 24-Pin QFN Pinout Diagram
Terminal List Table
Name
VIN
SS
SLEEP
GND
SYNC
POK
FSET
NC
COMP
FB
TEST
VREG
SW
BOOT
PAD
Number
1, 2
3
4
5, 16
6
7
8
9-11, 20-24
12
13
14
15
17, 18
19
‒
Function
Power input for the control circuits and the drain of the high-side N-channel MOSFET. Connect this pin to a power
supply providing from 4.0 to 35 V. A ceramic capacitor should be placed and grounded very close to this pin.
Soft start and hiccup pin. Connect a capacitor, C
SS
, from this pin to GND to set soft start mode duration. The capacitor
also determines the hiccup period during overcurrent.
Setting this pin low forces sleep mode (very low current shutdown mode: V
OUT
= 0 V). This pin must be set high to
enable the ARG81801. If the application does not require a sleep mode, then this pin can be tied directly to VIN. Do not
float this pin.
Ground pins.
Applying an external clock input to this pin forces synchronization of PWM to the clock input rate (f
SYNC
), at a rate higher
than f
OSC
. SLEEP low overrides this pin.
Power OK output signal. This pin is an open drain output that transitions from low to high impedance after the output
has maintained regulation for t
d(POK)
, typically 26 µs.
Frequency setting pin. A resistor, R
FSET
, from this pin to GND sets the base PWM switching frequency (f
OSC
). See the
Design and Component Selection section for information on determining the value of R
FSET
.
No connect pins. These should be connected to ground to aid thermal transfer.
Output of the error amplifier and compensation node for the current mode control loop. Connect a series RC network
from this pin to GND for loop compensation. See the Design and Component Selection section of this datasheet for
further details.
Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulator output, V
OUT
, to this pin to
program the output voltage.
Test mode pin. This pin should be connected to ground. Allegro recommends using a resistor from this pin to ground to
limit the regulator output voltage in the event the FB pin becomes shorted to this pin.
Internal voltage regulator bypass capacitor pin. Connect a 1 μF ceramic capacitor from this pin to ground and place it
close to the ARG81801.
The source of the high-side N-channel MOSFET. The external free-wheeling diode (D
1
) and output inductor (L
O
) should
be connected to this pin. Both D
1
and L
O
should be placed close to this pin and connected with relatively wide traces.
High-side gate drive boost input. This pin supplies the drive for the high-side N-channel MOSFET. Connect a 47 nF
ceramic capacitor from BOOT to SW.
Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground
plane(s) of the PCB with at least 6 vias, directly in the pad land.
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