Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm
2
/mg)
Packaging options:
- 48-lead flatpack
Standard Microcircuit Drawing 5962-01534
- QML Q and V compliant part
Compatible with TIA/EIA-644 LVDS standard
INTRODUCTION
The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel
with the data streams over a fourth LVDS link. Every cycle of
the transmit clock 21 bits of input data are sampled and
transmitted.
At a transmit clock frequency of 75MHz, 21 bits of TTL data
are transmitted at a rate of 525 Mbps per LVDS data channel.
Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197
Mbytes/sec).
The UT54LVDS217 Serializer allows the use of wide, high
speed TTL interfaces while reducing overall EMI and cable size.
All pins have Cold Spare buffers. These buffers will be high
impedance when V
DD
is tied to V
SS
.
21
CMOS/TTL INPUTS
TTL PARALLEL-TO-LVDS
TTL PARALLEL -TO-LVDS
DATA (LVDS)
TRANSMIT CLOCK IN
POWER DOWN
PLL
CLOCK (LVDS)
Figure 1. UT54LVDS217 Serializer Block Diagram
1
TxIN4
V
DD
TxIN5
TxIN6
GND
TxIN7
TxIN8
V
DD
TxIN9
TxIN10
GND
TxIN11
TxIN12
V
DD
TxIN13
TxIN14
GND
TxIN15
TxIN16
TxIN17
V
DD
TxIN18
TxIN19
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
UT54LVDS217
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TxIN3
TxIN2
GND
TxIN1
TxIN0
N/C
LVDS GND
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
LVDS V
DD
LVDS GND
TxOUT2-
TxOUT2+
TxCLK OUT-
TxCLK OUT+
LVDS GND
PLL GND
PLL V
DD
PLL GND
PWR DWN
TxCLK IN
TxIN20
PIN DESCRIPTION
Pin Name
TxIN
TxOUT+
TxOUT-
TxCLK IN
TxCLK
OUT+
TxCLK OUT-
PWR DWN
I/O
I
O
O
I
O
O
I
No.
21
3
3
1
1
1
1
Description
TTL level input
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The rising edge acts
as data strobe. Pin name TxCLK IN
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-
STATEs the clock and data outputs, ensur-
ing low current at power down.
Power supply pins for TTL inputs and logic
Ground pins for TTL inputs and logic
Power supply pins for PLL
Ground pins for PPL
Power supply pin for LVDS output
Ground pins for LVDS outputs
V
DD
GND
PLL V
DD
PLL GND
LVDS V
DD
LVDS GND
I
I
I
I
I
I
4
5
1
2
1
3
Figure 2. UT54LVDS217 Pinout
UT54LVDS217
TxIN
0
1
2
LVDS CABLE
MEDIA DEPENDENT DATA
(LVDS)
UT54LVDS218
RxOUT
0
1
2
CMOS/
TTL
18
19
20
18
19
20
CLOCK
(LVDS)
TxCLK
GND
PCB
SHIELD
Figure 3. UT54LVDS217 Typical Application
PCB
RxCLK
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
4
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 4.0V
-0.3 to (V
DD
+ 0.3V)
-65 to +150°C
2W
+150°C
10°C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and lifetest.
3. Test per MIL-STD-883, Method 1012.
4. For cold spare mode (V
DD
= V
SS
), V
I/O
may be 0.3V to the maximum recommended operating V
DD
+ 0.3V.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD,
P
LL
V
DD,
LVDS V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
3.0 to 3.6V
-55 to +125°C
0V to V
DD
3
DC ELECTRICAL CHARACTERISTICS
1
SYMBOL
PARAMETER
(V
DD
= 3.3V-0.3V; -55°C < T
C
< +125°C)
CONDITION
MIN
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS
V
IH
V
IL
I
IH
I
IL
V
CL
I
CS
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input clamp voltage
Cold Spare Leakage current
V
IN
= 3.6V; V
DD
= 3.6V
V
IN
= 0V; V
DD
= 3.6V
I
CL
= -18mA
V
IN
= 3.6V; V
DD
= V
SS
-20
2.0
GND
-10
-10
V
DD
0.8
+10
+10
-1.5
+20
V
V
µA
µA
V
µA
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
V
OD5
∆V
OD5
V
OS5
∆V
OS5
I
OZ4
I
CSOUT
I
OS2,3
Differential Output Voltage
Change in V
OD
between
complimentary output states
Offset Voltage
R
L
= 100Ω (See Figure 14)
R
L
= 100Ω (See Figure 14)
Voh + Vol
-
R
L
= 100Ω,
⎛
Vos = --------------------------
⎞
⎝
⎠
2
250
400
35
mV
mV
V
1.120
1.410
Change in V
OS
between
complimentary output states
Output Three-State Current
R
L
= 100Ω
PWR DWN = 0V
V
OUT
= 0V or V
DD
V
IN
=3.6V, V
DD
= V
SS
V
OUT
+ or V
OUT-
= 0V
-10
35
+10
mV
µΑ
µΑ
mA
Cold Spare Leakage Current
Output Short Circuit Current
-20
+20
5mA
Supply Current
I
CCL4
I
CCZ4,6
Transmitter supply current with
loads
Power down current
R
L
= 100Ω all channels
(figure 4)
CL = 5pF, f = 50MHz
D
IN
= V
SS
PWR DWN = 0V, f = 0Hz
65.0
mA
60.0
µA
Notes:
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, for a maximum
duration of one second.
3. Guaranteed by characterization.
4. Devices are tested @ 3.6V only.
5. Clock outputs guaranteed by design.
6. Post 100Krad and 300Krad, I
CCZ
= 200µA.
4
AC SWITCHING CHARACTERISTICS
1
(V
DD
= 3.0V to 3.6V; TA = -55°C to +125°C)
SYMBOL
LLHT
2
LHLT
2
TPPos0
2
TPPos1
2
TPPos2
2
TPPos3
2
TPPos4
2
TPPos5
2
TPPos6
2
TCCS
3
TCIP
TCIH
4
TCIL
4
TSTC
2
THTC
2
TCCD
TPLLS
TPDD
PARAMETER
LVDS Low-to-High Transition Time (Figure 5)
LVDS High-to-Low Transition Time (Figure 5)
Transmitter Output Pulse Position for Bit 0 (Figure 13)
Transmitter Output Pulse Position for Bit 1(Figure 13)
Transmitter Output Pulse Position for Bit 2 (Figure 13)
Transmitter Output Pulse Position for Bit 3 (Figure 13)
Transmitter Output Pulse Position for Bit 4 (Figure 13)
Transmitter Output Pulse Position for Bit 5 (Figure 13)
Transmitter Output Pulse Position for Bit 6 (Figure 13)
Channel to Channel skew (Figure 7)
TxCLK IN Period (Figure 8)
TxCLK IN High Time (Figure 8)
TxCLK IN Low Time (Figure 8)
TxIN Setup to TxCLK IN (Figure 8)
TxIN Hold to TxCLK IN (Figure 8)
TxCLK IN to TxCLK OUT Delay (Figure 9)
Transmitter Phase Lock Loop Set (Figure 10)
Transmitter Powerdown Delay (Figure 12)
15MHz
75MHz
15MHz
75MHz
13.3
0.35Tcip
0.35Tcip
1.0
0.5
0.7
0.5
0.5
2.5
10
100
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
-0.18
1.72
3.63
5.53
7.44
9.34
11.25
MIN
MAX
1.5
1.5
0.270
2.17
4.08
5.98
7.89
9.79
11.70
0.45
66.7
0.65Tcip
0.65Tcip
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Notes:
1. Recommend transistion time for TXCLK In is 1.0 to 6.0 ns (figure 6).
2. Guaranteed by characterization.
3. Channel to channel skew is defined as the difference between TPPOS max limit and TPPOS minimum limit.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
