Standard Products
UT54ACS299E
RadHard CMOS 8-bit Universal Shift/Storage Register
with Three-State Outputs
Datasheet
January, 2007
www.aeroflex.com/radhard
FEATURES
•
•
•
•
•
•
Common parallel I/O for reduced pin count
Additional serial inputs and outputs for expansion
Three-state outputs for bus-oriented applications
Operate with outputs enabled or at high impedance
Four operating modes: shift left, shift right, load and store
Can be cascaded for n-bit word lengths
LOGIC SYMBOL
MR
OE1
OE2
(9)
(2)
0
1
R
&
SRG8
3EN13
M 0
3
C4/1
/2
(8)
(3)
S0 (1)
S1 (19)
CP (12)
•
0.6μm Commercial RadHard
TM
CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU Onset LET: 95 MeV-cm
2
/mg (4.5V) and
•
48MeV-cm
2
/mg (3.0V)
Applications:
- Stacked or push-down registers
- Buffer storage
- Accumulator registers
Output source/sink 24mA
Available QML Q or V processes
Standard Microcircuit Drawing 5962-06238
Package:
- 20-lead flatpack
DS0 (11)
I00
(7)
1, 4D
3, 4D
5, 13
Z5
Z6
3, 4D
6, 13
Q0
I01 (13)
I02
I04
I06
(6)
(5)
(4)
I03 (14)
I05 (15)
I07 (16)
DS7
(18)
3, 4D
12, 13
2, 4D
•
•
•
•
Z12
(17)
Q7
DESCRIPTION
The UT54ACS299E 8-bit shift/storage register is built using
Aeroflex’s Commercial RadHard
TM
epitaxial CMOS technolo-
gy and is ideal for space applications. The UT54ACS299E is an
8-bit universal shift/storage register featuring multiplexed I/O
ports to achieve full 8-bit data handling in a single 20-pin pack-
age. Two function-select (S0, S1) inputs and two output enable
(OE1, OE2) inputs can be used to choose the mode of operation
listed in the function table. Additional outputs are provided for
flip flops Q0, Q7 to allow easy serial cascading. A separate
active low master reset (MR) is used to reset the register, over-
riding the select and CP inputs. All flip-flops are brought out
through three-state buffers to separate I/O pins that also serve
as data inputs in the parallel load mode. All other state changes
are initiated by the rising edge of the clock.
PIN DESCRIPTION
Pin Names
CP
DS0
DS7
S0, S1
MR
OE1, OE2
IO0-IO7
Q0, Q7
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
Three-State Output Enable Inputs
Parallel Data Inputs or Three-State Parallel Out-
puts
Serial Outputs
Description
1
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEL Immune
SEU Onset LET - 3.0V
SEU Onset LET - 4.5V
SEU Error Rate - 3.0V
2
SEU Error Rate - 4.5V
2
Neutron Fluence
3
LIMIT
1.0E5
>108
48
95
1.4E-8
8.1E-10
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
errors/device-day
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Adam’s 90% worst case particle environment, geosynchronous orbit, 100 mils aluminum shielding.
3. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/O
V
DD
T
STG
T
J
Θ
JC
I
I
P
D
PARAMETER
Voltage any pin during operation
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-.3 to V
DD
+.3
-0.3 to 6.0
-65 to +150
+175
20
±10
200
UNITS
V
V
°C
°C
°C/W
mA
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
t
INRISE
t
INFALL
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
Maximum input rise or fall time
(V
IN
transitioning between V
IL
(max) and V
IH
(min))
LIMIT
3.0 to 5.5
0 to V
DD
-55 to + 125
20
UNITS
V
V
°C
ns
4
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