INTEGRATED CIRCUITS
CBTD3306
Dual bus switch with level shifting
Product data
File under Integrated Circuits — ICL03
2001 Nov 08
Philips
Semiconductors
Philips Semiconductors
Product data
Dual bus switch with level shifting
CBTD3306
FEATURES
•
Designed to be used in 5 V to 3.3 V level shifting applications with
internal diode.
PIN CONFIGURATION
1OE
1A
1B
GND
1
2
3
4
8
7
6
5
V
CC
2OE
2B
2A
•
5
Ω
switch connection between two ports
•
TTL-compatible input levels
•
Package options include plastic small outline (SO) and
thin shrink small outline (TSSOP)
•
Latch-up protection exceeds 100 mA per JESD78
•
ESD protection exceeds 2000 V HBM per JESD22-A114 and
1000 V CDM per JESD22-C101
SA00535
PIN DESCRIPTION
PIN NUMBER
SYMBOL
1OE, 2OE
1A, 2A
1B, 2B
GND
V
CC
NAME AND FUNCTION
Output enable
A port inputs
B port outputs
Ground (0V)
Positive supply voltage
1, 7
2, 5
3, 6
4
8
DESCRIPTION
The CBTD3306 Dual FET Bus Switch features independent line
switches. Each switch is disabled with the associated Output Enable
(OE) input is high.
The CBTD3306 is characterized for operation from –40 to +85
°C.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IO(OFF)
I
CC
Propagation delay
A to B or B to A
Pin capacitance (OFF state)
Quiescent supply current
PARAMETER
CONDITIONS
T
amb
= 25
°C;
GND = 0 V
C
L
= 50 pF; V
CC
= +5.0 V
±0.5
V
V
O
= 3 V or 0; OE = V
CC
V
CC
= 5.5 V; I
O
= 0, V
I
= V
CC
or GND
TYPICAL
0.25 (MAX)
6.50
3
UNIT
ns
pF
µA
ORDERING INFORMATION
PACKAGES
8-pin plastic SO
8-pin plastic TSSOP
TEMPERATURE RANGE
–40 to 85
°C
–40 to 85
°C
ORDER CODE
CBTD3306D
CBTD3306PW
DWG NUMBER
SOT96-1
SOT530-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
LOGIC DIAGRAM (positive logic)
1A
2
3
1B
FUNCTION TABLE
INPUT
OE
L
H
6
FUNCTION
A port = B port
Disconnect
1OE
1
2A
5
2B
2OE
7
SA00534
2001 Nov 08
2
853-2305 27313
Philips Semiconductors
Product data
Dual bus switch with level shifting
CBTD3306
ABSOLUTE MAXIMUM RATINGS
1
T
amb
= –40 to +85
°C,
unless otherwise specified.
SYMBOL
V
CC
V
I
I
OUT
I
IK
T
stg
PARAMETER
DC supply voltage
DC input voltage
2
DC output current
Input diode current
Storage temperature range
V
I/O
< 0
CONDITIONS
RATING
–0.5 to +7.0
–0.5 to +7.0
128
–50
–65 to +150
UNIT
V
V
mA
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
V
CC
V
IH
V
IL
T
amb
DC supply voltage
High-level input voltage
Low-level Input voltage
Operating free-air temperature range
PARAMETER
LIMITS
MIN
4.5
2.0
—
–40
MAX
5.5
—
0.8
+85
UNIT
V
V
V
°C
NOTE:
1. All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
DC ELECTRICAL CHARACTERISTICS
T
amb
= –40 to +85
°C,
unless otherwise specified.
LIMITS
SYMBOL
V
IK
I
I
I
CC
V
P
∆I
CC
C
I
C
IO(OFF)
r
on 3
PARAMETER
Input clamp voltage
Input leakage current
Quiescent supply current
Output high pass voltage
Additional supply current per input pin
2
Control pins capacitance
Port off capacitance
On-resistance
TEST CONDITIONS
V
CC
= 4.5 V; I
I
= –18 mA
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; I
O
= 0, V
I
= V
CC
or GND
See Figure 1
V
CC
= 5.5 V, one input at 3.4 V,
other inputs at V
CC
or GND
V
I
= 3 V or 0
V
O
= 3 V or 0; OE = V
CC
V
CC
= 4.5 V; V
I
= 0V; I
I
= 64 mA
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 30 mA
V
CC
= 4.5 V; V
I
= 2.4 V; I
I
= 15 mA
T
amb
= –40 to +85
°C
MIN
—
—
—
—
—
—
—
—
—
—
TYP
1
—
—
—
—
—
3.20
6.50
3.6
3.6
17
MAX
–1.2
±1
1.5
—
2.5
—
—
5
5
35
V
µA
mA
V
mA
pF
pF
Ω
Ω
Ω
UNIT
NOTES:
1. All typical values are at V
CC
= 5 V, T
amb
= 25
°C.
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
2001 Nov 08
3
Philips Semiconductors
Product data
Dual bus switch with level shifting
CBTD3306
AC CHARACTERISTICS
T
amb
= –40 to +85
°C;
C
L
= 50 pF
LIMITS
SYMBOL
t
pd
t
en
t
dis
PARAMETER
Propagation delay
1
Output enable time
to High and Low level
Output disable time
from High and Low level
FROM (INPUT)
A or B
OE
OE
TO
(OUTPUT)
B or A
A or B
A or B
V
CC
= +5.0 V
±0.5
V
MIN
—
1
1
MAX
0.25
5
4.9
ns
ns
ns
UNIT
NOTE:
1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
3V
1.5 V
INPUT
0V
t
PLH
t
PHL
V
OH
1.5 V
OUTPUT
V
OL
1.5 V
1.5 V
TEST CIRCUIT AND WAVEFORMS
7V
From Output
Under Test
C
L
= 50 pF
500
Ω
S1
Open
GND
500
Ω
Load Circuit
TEST
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
open
7V
open
SA00028
Waveform 1. Input to Output Propagation Delays
DEFINITIONS
Load capacitance includes jig and probe capacitance;
C
L
=
see AC CHARACTERISTICS for value.
3V
Output Control
(Low-level
enabling )
t
PZL
Output
Waveform 1
S1 at 7 V
(see Note)
t
PZH
Output
Waveform 2
S1 at Open
(see Note)
1.5 V
1.5 V
0V
3.5 V
1.5 V
t
PHZ
V
OH
– 0.3 V
1.5 V
0V
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
SA00012
t
PLZ
NOTES:
1. All input pulses are supplied by generators having the following
characteristics: PRR
≤
10 MHz, Z
O
= 50
Ω,
t
r
≤
2.5 ns, t
f
≤
2.5 ns.
2. The outputs are measured one at a time with one transition per
measurement.
V
OL
+ 0.3 V
V
OL
V
OH
SA00029
Waveform 2. 3-State Output Enable and Disable Times
NOTES:
1. t
PLZ
and t
PHZ
are the same as t
dis
.
2. t
PZL
and t
PZH
are the same as t
en
.
3. t
PLH
and t
PHL
are the same as t
pd
.
2001 Nov 08
4
Philips Semiconductors
Product data
Dual bus switch with level shifting
CBTD3306
Temp = 85
°C
3.8
3.6
3.4
V
P
3.2
3.0
6 mA
12 mA
24 mA
3.0
V
P
3.2
100
µA
3.8
3.6
Temp = 70
°C
100
µA
3.4
6 mA
12 mA
24 mA
2.8
2.8
2.6
2.6
2.4
2.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
V
CC
– Supply Voltage
2.4
2.2
4.4
Temp = 25
°C
3.6
100
µA
4.6
4.8
5.0
5.2
5.4
5.6
V
CC
– Supply Voltage
3.4
3.2
6 mA
V
P
3.0
12 mA
24 mA
2.8
2.6
2.4
2.2
4.4
Temp = 0
°C
3.6
100
µA
3.4
3.2
3.2
6 mA
12 mA
3.0
V
P
2.8
2.6
2.6
2.4
2.4
2.2
2.0
4.4
4.6
4.8
5.0
5.2
5.4
5.6
V
CC
– Supply Voltage
V
CC
– Supply Voltage
2.2
2.0
4.4
4.6
4.8
5.0
5.2
5.4
5.6
24 mA
V
P
3.0
12 mA
24 mA
2.8
4.6
4.8
5.0
5.2
5.4
5.6
V
CC
– Supply Voltage
Temp = –40
°C
100
µA
3.4
6 mA
SW00895
Figure 1. Pass voltage values (V
in
= V
CC
)
2001 Nov 08
5
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