IS61SP12832
128K x 32 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin LQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
DESCRIPTION
The
ICSI
IS61SP12832 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 131,072
words by 32 bits, fabricated with
ICSI
's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls DQc,
BW4
controls DQd, conditioned by
BWE
being LOW. A LOW
on
GW
input would cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP12832 and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frenquency
-166
3.5
6
166
-150
3.8
6.7
150
-133
4
7.5
133
-117
4
8.5
117
-5
5
10
100
Units
ns
ns
MHz
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SSR011-0B
1
IS61SP12832
BLOCK DIAGRAM
MODE
Q0
A0’
CLK
CLK
A0
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1’
A1
128K x 32
MEMORY
ARRAY
15
17
A16-A0
17
D
Q
ADDRESS
REGISTER
CE
CLK
32
32
GW
BWE
BW4
DQd
BYTE WRITE
REGISTERS
CLK
D
Q
BW3
DQc
Q
BYTE WRITE
REGISTERS
CLK
D
BW2
DQb
BYTE WRITE
REGISTERS
CLK
D
Q
BW1
DQa
Q
BYTE WRITE
REGISTERS
D
CLK
CE
CE2
CE2
D
Q
4
ENABLE
REGISTER
CE
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
32
DQ[31:0]
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Circuit Solution Inc.
SSR011-0B
IS61SP12832
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin LQFP
1
A
VCCQ
B
NC
C
NC
D
DQc1
E
DQc2
F
VCCQ
G
DQc5
H
DQc7
J
VCCQ
K
DQd1
L
DQd4
M
VCCQ
N
DQd6
P
DQd8
R
NC
T
NC
U
VCCQ
2
3
4
5
6
7
A6
CE2
A7
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
A5
NC
NC
A4
A3
A2
GND
GND
GND
BW3
GND
NC
GND
BW4
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BW2
GND
NC
GND
BW1
GND
GND
GND
NC
A14
NC
A16
CE2
A15
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCC
DQa2
DQa1
NC
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
DQa-DQd
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
Synchronous Clock
MODE
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
ZZ
GND
Q
V
CC
GND
V
CCQ
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V
Snooze Enable
Isolated Output Buffer Ground
Synchronous Data Input/Output
GW
OE
Synchronous Global Write Enable
CE, CE2,
CE2 Synchronous Chip Enable
Output Enable
A2-A16
Integrated Circuit Solution Inc.
SSR011-0B
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
3
IS61SP12832
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
X
X
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
X
L
X
0
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
H
H
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
0
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV WRITE
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
OE
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
Q
High-Z
High-Z
High-Z
Q
High-Z
Q
High-Z
High-Z
High-Z
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
BW1
X
H
L
L
X
BW2
X
H
H
L
X
BW3 BW4
X
H
H
L
X
X
H
H
L
X
4
Integrated Circuit Solution Inc.
SSR011-0B
IS61SP12832
INTERLEAVED BURST ADDRESS TABLE (MODE = V
CCQ
or No Connect)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND
Q
)
0,0
A1’, A0’ = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
T
BIAS
T
STG
P
D
I
OUT
V
IN
, V
OUT
V
IN
V
CC
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
Voltage on Vcc Supply Relatiive to GND
Value
–40 to +85
–55 to +150
1.6
100
–0.5 to V
CCQ
+ 0.3
–0.5 to V
CC
+ 0.5
–0.5 to 4.6
Unit
°C
°C
W
mA
V
V
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Circuit Solution Inc.
SSR011-0B
5
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