Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using ’trench’ technology
the device features very low on-state
resistance and has integral zener
diodes giving ESD protection up to
2kV. It is intended for use in
automotive and general purpose
switching applications.
BUK9628-55
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 5 V
MAX.
55
40
96
175
28
UNIT
V
A
W
˚C
mΩ
PINNING - SOT404
PIN
1
2
3
mb
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
40
28
160
96
175
UNIT
V
V
V
A
A
A
W
˚C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
Minimum footprint, FR4
board
TYP.
-
50
MAX.
1.56
-
UNIT
K/W
K/W
April 1998
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
(BR)GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
Gate-source breakdown
voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 55 V; V
GS
= 0 V;
V
GS
=
±5
V; V
DS
= 0 V
I
G
=
±1
mA;
V
GS
= 5 V; I
D
= 20 A
T
j
= 175˚C
T
j
= 175˚C
T
j
= 175˚C
MIN.
55
50
1
0.5
-
-
-
-
-
10
-
-
TYP.
-
-
1.5
-
-
0.05
-
0.02
-
22
-
BUK9628-55
MAX.
-
-
2
-
2.3
10
500
1
10
-
28
59
UNIT
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
g
fs
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
s
PARAMETER
Forward transconductance
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
CONDITIONS
V
DS
= 25 V; I
D
= 25 A
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
13
-
-
-
-
-
-
-
-
-
TYP.
-
1300
250
130
22
85
70
64
2.5
7.5
MAX.
-
1700
300
180
32
125
95
85
-
-
UNIT
S
pF
pF
pF
ns
ns
ns
ns
nH
nH
V
DD
= 30 V; I
D
= 25 A;
V
GS
= 5 V; R
G
= 10
Ω
Resistive load
Measured from upper edge of drain
tab to centre of die
Measured from source lead
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 40 A; V
GS
= 0 V
I
F
= 40 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
-
-
-
-
-
TYP.
-
-
0.95
1.0
41
0.16
MAX.
40
160
1.2
-
-
-
UNIT
A
A
V
ns
µC
April 1998
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 35 A; V
DD
≤
25 V;
V
GS
= 5 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
TYP.
-
BUK9628-55
MAX.
70
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1000
ID/A
RDS(ON) = VDS/ID
tp =
1 us
10us
100 us
1 ms
10ms
100ms
100
DC
10
0
20
40
60
80 100
Tmb / C
120
140
160
180
1
1
10
VDS/V
100
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Normalised Current Derating
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Zth/ (K/W)
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
10
1
0.5
0.2
0.1
P
D
t
p
D=
t
p
T
t
0.1
0.05
0.02
T
0
0
20
40
60
80 100
Tmb / C
120
140
160
180
0.01
1.0E-06
0.0001
0.01
t/s
1
100
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
April 1998
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
BUK9628-55
100
ID/A
80
10
8
6
5
VGS/V =
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
40
gfs/S
35
30
25
20
15
10
5
60
40
20
0
0
2
4
VDS/V
6
8
2.8
2.6
2.4
2.2
10 2.0
0
10
20
30
40
ID/A
50
60
70
80
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON)/mOhm
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
BUK959-60
34
32
2.5
4
VGS/V =
4.2
a
Rds(on) normlised to 25degC
30
28
26
24
22
20
2
4.4
4.6
4.8
5
1.5
1
0
10
20
30 ID/A 40
50
60
70
0.5
-100
-50
0
50
Tmb / degC
100
150
200
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
80
ID/A
70
60
50
40
30
20
10
0
0
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 20 A; V
GS
= 5 V
VGS(TO) / V
max.
2
typ.
1.5
min.
1
BUK959-60
2.5
0.5
Tj/C =
1
175
2
25
3
VGS/V
4
5
6
0
-100
-50
0
50
Tj / C
100
150
200
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
April 1998
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
BUK9628-55
1E-01
Sub-Threshold Conduction
100
IF/A
80
1E-02
2%
typ
98%
60
Tj/C =
40
175
25
1E-03
1E-04
1E-05
20
1E-05
0
0
0.5
1
1.5
2
2.5
3
0
0.5
VSDS/V
1
1.5
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
3
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
120
110
100
90
80
70
60
Ciss
2.5
Thousands pF
2
1.5
50
40
30
20
10
1
.5
0
0.01
Coss
Crss
100
0
20
40
60
80
100
120
Tmb / C
140
160
180
0.1
1
VDS/V
10
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
6
VGS/V
5
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 40 A
+
L
VDS = 14V
VDS = 44V
VDD
4
VDS
VGS
0
RGS
T.U.T.
R 01
shunt
3
-
-ID/100
2
1
0
0
5
10
15
QG/nC
20
25
30
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 40 A; parameter V
DS
Fig.16. Avalanche energy test circuit.
2
W
DSS
=
0.5
⋅
LI
D
⋅
BV
DSS
/(BV
DSS
−
V
DD
)
April 1998
5
Rev 1.100
FPGA/CPLD
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