BUK9240-100A
TrenchMOS™ logic level FET
Rev. 01 — 03 October 2000
Product specification
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™
1
technology, featuring very low on-state resistance.
Product availability:
BUK9240-100A in SOT428 (D-PAK).
2. Features
s
s
s
s
TrenchMOS™ technology
Q101 compliant
175
°C
rated
Logic level compatible.
3. Applications
c
c
s
Automotive and general purpose power switching:
x
12 V and 24 V loads
x
Motors, lamps and solenoids.
4. Pinning information
Table 1:
Pin
1
2
3
mb
Pinning - SOT428 (D-PAK), simplified outline and symbol
Description
gate (g)
mb
Simplified outline
Symbol
drain (d)
source (s)
mounting base;
connected to
drain (d)
g
2
1
Top view
3
MBK091
d
MBB076
s
SOT428 (D-PAK)
1.
TrenchMOS is a trademark of Royal Philips Electronics.
Philips Semiconductors
BUK9240-100A
TrenchMOS™ logic level FET
5. Quick reference data
Table 2:
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Conditions
T
mb
= 25
°C;
V
GS
= 5 V
T
mb
= 25
°C
V
GS
= 5 V; I
D
= 25 A
V
GS
= 4.5 V; I
D
= 25 A
Typ
−
−
−
−
34
−
Max
100
33
114
175
40
44.6
Unit
V
A
W
°C
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
Symbol Parameter
m
Ω
m
Ω
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
V
GSM
I
D
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
non-repetitive gate-source voltage
drain current (DC)
t
p
≤
50
µs
T
mb
= 25
°C;
V
GS
= 5 V;
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 5 V;
Figure 2
I
DM
P
tot
T
stg
T
j
I
DR
I
DRM
W
DSS
peak drain current
total power dissipation
storage temperature
operating junction temperature
reverse drain current (DC)
pulsed reverse drain current
non-repetitive avalanche energy
T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 25 A;
V
DS
≤
100 V; V
GS
= 5 V; R
GS
= 50
Ω;
starting T
j
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
mb
= 25
°C;
Figure 1
[1]
Conditions
R
GS
= 20 kΩ
Min
−
−
−
−
−
−
−
−
−55
−55
−
−
−
Max
100
100
±10
±15
33
23.8
135
114
+175
+175
33
135
31
Unit
V
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
[1]
I
DM
is limited by chip, not package.
9397 750 07573
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 01 — 03 October 2000
2 of 13
Philips Semiconductors
BUK9240-100A
TrenchMOS™ logic level FET
120
P
der
(%)
100
03aa16
03aa24
120
Ider
(%)
100
80
80
60
60
40
40
20
20
0
0
25
50
75
100
125
150
175
200
Tmb (oC)
0
0
25
50
75
100
125
150
175
200
Tmb (oC)
P
tot
P
der
=
----------------------
×
100%
P
°
tot
(
25 C
)
V
GS
≥
4.5 V
I
D
I
der
=
------------------
×
100%
-
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
1000
ID
(A)
RDSon = VDS / ID
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03na69
100
tp = 10 us
10
P
δ
=
tp
T
100 us
D.C.
tp
T
t
1 ms
10 ms
100 ms
1
1
10
100
VDS (V)
1000
T
amb
= 25
°C;
I
DM
is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 07573
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 01 — 03 October 2000
3 of 13
Philips Semiconductors
BUK9240-100A
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4:
Symbol
R
th(j-a)
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance from junction to ambient
thermal resistance from junction to mounting
base
Conditions
Figure 4
Value
71.4
1.3
Unit
K/W
K/W
7.1 Transient thermal impedance
10
Zth(j-mb)
(K/W)
1
0.5
0.2
0.1
03na70
0.1
0.05
0.02
P
δ
=
tp
T
0.01
Single Shot
tp
T
t
0.001
10-6
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of
pulse duration.
9397 750 07573
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 01 — 03 October 2000
4 of 13
Philips Semiconductors
BUK9240-100A
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
T
j
= 25
°
C unless otherwise specified
Symbol
V
(BR)DSS
Parameter
drain-source breakdown
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 175
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 100 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 175
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state
resistance
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 175
°C
V
GS
= 4.5 V; I
D
= 25 A;
T
j
= 25
°C
V
GS
= 10 V; I
D
=25 A;
T
j
=25°C
Dynamic characteristics
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off
)
t
f
L
d
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
measured from drain lead
from package to centre of
die
measured from source lead
from package to source
bond pad
V
DD
= 30 V; R
L
= 1.2
Ω;
V
GS
= 5 V; R
G
= 10
Ω
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz;
Figure 12
−
−
−
−
−
−
−
−
2304
222
151
20
135
125
90
2.5
3072
266.4
207
−
−
−
−
−
pF
pF
pF
ns
ns
ns
ns
nH
−
−
−
−
34
−
−
33
40
100
44.6
38.6
mΩ
mΩ
mΩ
mΩ
−
−
−
0.05
−
2
10
500
100
µA
µA
nA
1
0.5
−
1.5
−
−
2
−
2.3
V
V
V
100
89
−
−
−
−
V
V
Min
Typ
Max
Unit
Static characteristics
L
s
internal source inductance
−
7.5
−
nH
9397 750 07573
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 01 — 03 October 2000
5 of 13
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