Philips Semiconductors
Product specification
Thyristors
logic level
GENERAL DESCRIPTION
Passivated, sensitive gate thyristors in a
plastic envelope, intended for use in
general purpose switching and phase
control applications. These devices are
intended to be interfaced directly to
microcontrollers, logic integrated circuits
and other low power gate trigger circuits.
BT149 series
QUICK REFERENCE DATA
SYMBOL
V
DRM
, V
RRM
I
T(AV)
I
T(RMS)
I
TSM
PARAMETER
BT149
Repetitive peak
off-state voltages
Average on-state
current
RMS on-state current
Non-repetitive peak
on-state current
MAX.
B
200
0.5
0.8
8
MAX.
D
400
0.5
0.8
8
MAX.
G
600
0.5
0.8
8
UNIT
V
A
A
A
PINNING - TO92 variant
PIN
1
2
3
DESCRIPTION
cathode
gate
anode
PIN CONFIGURATION
SYMBOL
a
k
3 2 1
g
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
-
half sine wave;
T
lead
≤
83 ˚C
all conduction angles
t = 10 ms
t = 8.3 ms
half sine wave;
T
j
= 25 ˚C prior to surge
t = 10 ms
I
TM
= 2 A; I
G
= 10 mA;
dI
G
/dt = 100 mA/µs
-
-
-
-
-
-
-
-
-
-
-
-40
-
B
200
1
MAX.
D
400
1
0.5
0.8
8
9
0.32
50
1
5
5
2
0.1
150
125
G
600
1
UNIT
V
A
A
A
A
A
2
s
A/µs
A
V
V
W
W
˚C
˚C
V
DRM
, V
RRM
Repetitive peak off-state
voltages
I
T(AV)
I
T(RMS)
I
TSM
Average on-state current
RMS on-state current
Non-repetitive peak
on-state current
I
2
t
dI
T
/dt
I
GM
V
GM
V
RGM
P
GM
P
G(AV)
T
stg
T
j
I
2
t for fusing
Repetitive rate of rise of
on-state current after
triggering
Peak gate current
Peak gate voltage
Peak reverse gate voltage
Peak gate power
Average gate power
over any 20 ms period
Storage temperature
Operating junction
temperature
1
Although not recommended, off-state voltages up to 800V may be applied without damage, but the thyristor may
switch to the on-state. The rate of rise of current should not exceed 15 A/µs.
September 2001
1
Rev 1.500
Philips Semiconductors
Product specification
Thyristors
logic level
THERMAL RESISTANCES
SYMBOL
R
th j-lead
R
th j-a
PARAMETER
Thermal resistance
junction to lead
Thermal resistance
junction to ambient
pcb mounted; lead length = 4mm
CONDITIONS
MIN.
-
-
BT149 series
TYP.
-
150
MAX.
60
-
UNIT
K/W
K/W
STATIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
I
GT
I
L
I
H
V
T
V
GT
I
D
, I
R
PARAMETER
Gate trigger current
Latching current
Holding current
On-state voltage
Gate trigger voltage
Off-state leakage current
CONDITIONS
V
D
= 12 V; I
T
= 10 mA; gate open circuit
V
D
= 12 V; I
GT
= 0.5 mA; R
GK
= 1 kΩ
V
D
= 12 V; I
GT
= 0.5 mA; R
GK
= 1 kΩ
I
T
= 1 A
V
D
= 12 V; I
T
= 10 mA; gate open circuit
V
D
= V
DRM(max)
; I
T
= 10 mA; T
j
= 125 ˚C;
gate open circuit
V
D
= V
DRM(max)
; V
R
= V
RRM(max)
; T
j
= 125 ˚C;
R
GK
= 1 kΩ
MIN.
-
-
-
-
-
0.2
-
TYP.
50
2
2
1.2
0.5
0.3
0.05
MAX.
200
6
5
1.35
0.8
-
0.1
UNIT
µA
mA
mA
V
V
V
mA
DYNAMIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
dV
D
/dt
t
gt
t
q
PARAMETER
Critical rate of rise of
off-state voltage
Gate controlled turn-on
time
Circuit commutated
turn-off time
CONDITIONS
V
DM
= 67% V
DRM(max)
; T
j
= 125 ˚C;
exponential waveform; R
GK
= 1 kΩ
I
TM
= 2 A; V
D
= V
DRM(max)
; I
G
= 10 mA;
dI
G
/dt = 0.1 A/µs
V
D
= 67% V
DRM(max)
; T
j
= 125 ˚C;
I
TM
= 1.6 A; V
R
= 35 V; dI
TM
/dt = 30 A/µs;
dV
D
/dt = 2 V/µs; R
GK
= 1 kΩ
MIN.
500
-
-
TYP.
800
2
100
MAX.
-
-
-
UNIT
V/µs
µs
µs
September 2001
2
Rev 1.500
Philips Semiconductors
Product specification
Thyristors
logic level
BT149 series
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Ptot / W
conduction form
angle
factor
degrees
a
30
4
60
2.8
90
2.2
120
1.9
180
1.57
Tc(max) / C
77
a = 1.57
83
1.9
2.2
2.8
89
95
101
107
113
10
ITSM / A
IT
I TSM
8
time
T
Tj initial = 25 C max
6
4
4
2
119
0
0.1
0.2
0.3
0.4
IF(AV) / A
0.5
0.6
125
0.7
0
1
10
100
Number of half cycles at 50Hz
1000
Fig.1. Maximum on-state dissipation, P
tot
, versus
average on-state current, I
T(AV)
, where
a = form factor = I
T(RMS)
/ I
T(AV)
.
ITSM / A
Fig.4. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
1000
2
IT(RMS) / A
1.5
100
1
10
IT
T
I TSM
0.5
time
Tj initial = 25 C max
1
10us
100us
T/s
1ms
10ms
0
0.01
0.1
surge duration / s
1
10
Fig.2. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus pulse width t
p
, for
sinusoidal currents, t
p
≤
10ms.
IT(RMS) / A
Fig.5. Maximum permissible repetitive rms on-state
current I
T(RMS)
, versus surge duration, for sinusoidal
currents, f = 50 Hz; T
lead
≤
83˚C.
VGT(Tj)
VGT(25 C)
1
1.6
83 C
0.8
1.4
1.2
1
0.6
0.4
0.8
0.2
0.6
0
50
Tlead / C
100
150
0
-50
0.4
-50
0
50
Tj / C
100
150
Fig.3. Maximum permissible rms current I
T(RMS)
,
versus lead temperature, T
lead
.
Fig.6. Normalised gate trigger voltage
V
GT
(T
j
)/ V
GT
(25˚C), versus junction temperature T
j
.
September 2001
3
Rev 1.500
Philips Semiconductors
Product specification
Thyristors
logic level
BT149 series
3
2.5
2
1.5
IGT(Tj)
IGT(25 C)
5
IT / A
Tj = 125 C
Tj = 25 C
4
Vo = 1.067 V
Rs = 0.187 ohms
typ
max
3
2
1
1
0.5
0
-50
0
0
0.5
1
VT / V
1.5
2
2.5
0
50
Tj / C
100
150
Fig.7. Normalised gate trigger current
I
GT
(T
j
)/ I
GT
(25˚C), versus junction temperature T
j
.
IL(Tj)
IL(25 C)
Fig.10. Typical and maximum on-state characteristic.
100
Zth j-lead (K/W)
3
2.5
2
10
1
1.5
1
0.5
0
-50
0.01
10us
0.1ms
1ms
10ms
tp / s
0.1s
1s
P
D
tp
0.1
t
0
50
Tj / C
100
150
10s
Fig.8. Normalised latching current I
L
(T
j
)/ I
L
(25˚C),
versus junction temperature T
j
, R
GK
= 1 kΩ.
IH(Tj)
IH(25 C)
Fig.11. Transient thermal impedance Z
th j-lead
, versus
pulse width t
p
.
dVD/dt (V/us)
10000
3
2.5
RGK = 1 kohms
1000
2
1.5
1
0.5
0
-50
10
0
50
100
150
100
0
50
Tj / C
100
150
Tj / C
Fig.9. Normalised holding current I
H
(T
j
)/ I
H
(25˚C),
versus junction temperature T
j
, R
GK
= 1 kΩ.
Fig.12. Typical, critical rate of rise of off-state voltage,
dV
D
/dt versus junction temperature T
j
.
September 2001
4
Rev 1.500
Philips Semiconductors
Product specification
Thyristors
logic level
MECHANICAL DATA
Plastic single-ended leaded (through hole) package; 3 leads
BT149 series
SOT54
c
E
d
A
L
b
1
D
2
e1
e
3
b
1
L1
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
5.2
5.0
b
0.48
0.40
b1
0.66
0.56
c
0.45
0.40
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
e
2.54
e1
1.27
L
14.5
12.7
L1
(1)
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54
REFERENCES
IEC
JEDEC
TO-92
EIAJ
SC-43
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
Fig.13. TO92 ; plastic envelope; Net Mass: 0.2 g
Notes
1. Epoxy meets UL94 V0 at 1/8".
September 2001
5
Rev 1.500
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