1M
X28C010
5 Volt, Byte Alterable E
2
PROM
DESCRIPTION
128K x 8 Bit
FEATURES
• Access Time: 120ns
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V
PP
Control Cir-
cuits
—Self-Timed
• No Erase Before Write
• No Complex Programming Algorithms
• No Overerase Problem
• Low Power CMOS:
—Active: 50mA
—Standby: 500µA
• Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
• Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
PIN CONFIGURATIONS
CERDIP
FLAT PACK
SOIC (R)
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X28C010
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
The Xicor X28C010 is a 128K x 8 E
2
PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard
EPROMs.
The X28C010 supports a 256-byte page write operation,
effectively providing a 19µs/byte write cycle and enabling
the entire memory to be typically written in less than 2.5
seconds. The X28C010 also features DATA Polling and
Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C010 supports Software Data Protection
option.
Xicor E
2
PROMs are designed and tested for applications
requiring extended endurance. Data retention is specified
to be greater than 100 years.
A12
A15
A16
NC
VCC
4 3 2
1
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
A7
A6
A5
A4
A3
A2
A1
A0
I/O 0
5
6
7
8
9
10
11
12
13
30
29
28
27
26
25
24
23
22
NC
VCC
A 12
A 15
A 16
WE
NC
PGA
I/O6
I/O0
I/O2
I/O 3
I/O5
22
15
17
19
21
A1
13
A2
12
A4
10
A6
A12
6
5
A
16
A0
14
A3
11
9
A5
A7
A15
2
NC
3
NC
VCC
NC
34
36
NC
1
WE
35
X28C010
(BOTTOM VIEW)
CE
I/O4
I/O7
I/O1
VSS
24
20
23
16
18
A10
OE
25
26
A11
27
A8
29
NC
32
NC
33
A9
28
A 13
30
A 14
31
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
32 31 30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
54 3 2
6
7
32 31
1
8
X28C010
9
(TOP VIEW)
10
11
12
13
15 16 17 18 19 20 21
14
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
X28C010
(TOP VIEW)
8
7
14 15 16 17 18 19 20
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
TSOP
4
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X28C010
????-1.0 2/12/99 ??/??/?? EP
1
Characteristics subject to change without notice
WE
NC
PLCC
LCC
EXTENDED LCC
X28C010
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture
eliminates bus contention in a system environment. The
data bus will be in a high impedance state when either
OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010 supports both a
CE and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first. A
byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows two
to two hundred fifty-six bytes of data to be consecutively
written to the X28C010 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A
8
through A
16
) for each subsequent valid
write cycle to the part during this operation must be the
same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28C010 provides the user two write operation
status bits. These can be used to optimize a system write
cycle time. The status bits are mapped onto the I/O bus
as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
DATA Polling (I/O
7
)
The X28C010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C010,
eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O
7
(i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
7
will reflect true data. Note: If the
X28C010 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
Toggle Bit (I/O
6
)
The X28C010 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
X28C010
The Toggle Bit I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
VOH
*
VOL
I/O6
HIGH Z
*
X28C010
READY
* Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
NO
READY
5
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