The UT54ACS138 and the UT54ACTS138 3-line to 8-line de-
coders/demultiplexers are designed to be used in high-perfor-
mance memory-decoding or data-routing applications requiring
very short propagation delay times.
The conditions at the binary select inputs and the three enable
inputs select one of eight output lines. Two active-low and one
active-high enable inputs reduce the need for external gates of
inverters when expanding. A 24-line decoder can be implement-
ed without external inverters and a 32-line decoder requires only
one inverter. An enable input can be used as a data input for
demultiplexing applications.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
ENABLE INPUTS
G1
X
L
X
H
H
H
H
H
H
H
H
G2A
X
X
H
L
L
L
L
L
L
L
L
G2B
H
X
X
L
L
L
L
L
L
L
L
C
X
X
X
L
L
L
L
H
H
H
H
SELECT INPUTS
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
Y0
H
H
H
L
H
H
H
H
H
H
H
PINOUTS
16-Pin DIP
Top View
A
B
C
G2A
G2B
G1
Y7
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
16-Lead Flatpack
Top View
A
B
C
G2A
G2B
G1
Y7
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
OUTPUT
Y1
H
H
H
H
L
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
1
H
H
LOGIC SYMBOL
(1)
BIN/OCT
1
2
4
0
1
2
3
4
G1
G2A
G2B
(6)
(4)
(5)
&
EN
5
6
7
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(7)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G2B
G1
G2A
(6)
(4)
(5)
&
EN
A
B
C
(1)
(2)
(3)
DMUX
1
2
4
A
B (2)
(3)
C
0
G
---
7
0
1
2
3
4
5
6
7
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(7)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Note:
1. Logic symbols in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM
(15)
(14)
G1
ENABLE
(6)
Y0
Y1
G2A (4)
G2B (5)
(13) Y2
(12)
(11)
(10)
Y3
DATA
Y4
Y5
Y6
Y7
A
SELECT
B
(1)
(2)
(9)
(7)
C (3)
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
3
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
ΔI
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100μA
I
OH
= -8.0mA
I
OH
= -100μA
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
15
15
pF
pF
1.9
10
1.6
mW/
MHz
μA
mA
-8
mA
.7V
DD
V
DD
- 0.25
-200
8
200
.5V
DD
.7V
DD
-1
1
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
μA
0.40
0.25
V
V
OH
V
I
OS
I
OL
mA
mA
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
出版业曾经流传着一个笑话：如果您的出版品面临困境之际，就重新改版设计吧！然而，这句话在目前一点也起不了作用了；当今的出版事业如果未能发展网路服务，那就免不了完全倒闭一途。零售业也有这样必然的结果吗？
Best Buy重新布局旗下60家零售商店了。这家电子零售商重新配置其庞大的电子商场，使其看起来更像是一家…...苹果零售店(Apple Stores)。在此之前，Best B...[详细]
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
