µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
June 2009
FIN210AC
10-Bit Serializer / Deserializer Supporting Cameras and
Small Displays up to 48MHz
Features
Data & Control Bits
Frequency
Capability
Interface
µController Usage
Selectable Edge Rates
Standby Current
Core Voltage (V
DDA/S
)
I/O Voltage (V
DDP
)
ESD (I/O to GND)
Package
Ordering Information
10-bit
48MHz
Camera or LCD
Microcontroller, RGB, YUV
m68 & i86
Yes
<10µA
2.8 to 3.6V
1.65 to 3.6V
15kV
32-Terminal MLP (Preliminary)
42-Ball USS-BGA
FIN210ACMLX (Preliminary)
FIN210ACGFX
Description
The FIN210AC µSerDes™ is a low-power serializer /
deserializer optimized for use in cell phone displays and
camera paths. The device reduces a 10-bit data path to four
wires. For camera applications, an additional master clock
can be passed in the opposite direction of data flow. The
device utilizes Fairchild’s proprietary ultra-low power, low-
EMI technology.
Applications
Slider, Folder, & Clamshell Mobile Handsets
Printers
Security Cameras
Related Resources
For samples and questions, please contact:
Interface@fairchildsemi.com.
Typical Application
Internal
Termination
Built-in voltage
translation
FIN210AC
+
-
FIN210AC
2
2
+
-
10-Bit Serializer
12-Bit Serializer
Camera
Module
10-Bit
12-Bit
Des erializer
Des erializer
Baseband
+
-
+
-
CTL™
Isolates interface
for signal integrity
Up to 48MHz
Camera
Module
Figure 1. Mobile Phone Example
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
www.fairchildsemi.com
µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
FIN210AC (Serializer DIRI=1) Pin Descriptions
Pin Name
DIRI
CTL_ADJ
S0
S1
PLL0
PLL1
CKREF
STROBE
DP[1:10]
CKSO+
CKSO-
DSO+
DSO-
CKSI+
CKSI-
CKP
/DIRO
VDDP
VDDS
VDDA
GND
N/C
Description
Control to determine serializer or deserializer configuration.
Adjusts CTL drive to compensate for environmental conditions
and length.
Configure frequency range for the PLL.
Configure frequency range for the PLL.
Divide or adjust the serial frequency.
0 Deserializer
1 Serializer
0 Low drive (low power)
1 High drive (high power)
See Table 1 Serializer (DIRI=1) Control Pin.
See Table 1 Serializer (DIRI=1) Control Pin.
See Table 1 Serializer (DIRI=1) Control Pin.
Divide or adjust the serial frequency.
See Table 1 Serializer (DIRI=1) Control Pin.
LV-CMOS clock input and PLL reference.
LV-CMOS strobe input for latching data (DP [1:12]) into the serializer on the rising edge.
LV-CMOS parallel data input. (GND input if not used)
CTL Differential serializer output bit clock.
CKSO+: Positive signal; CKSO-: Negative signal.
CTL Differential serial output data signals.
DSO+: Positive signal; DSO-: Negative signal.
CTL Differential deserializer input bit clock.
No connect unless in “clock pass-through” mode.
CKSI+: Positive signal; CKSI-: Negative signal.
LV-CMOS word clock output or Pixel clock output.
No connect unless in “clock pass-through” mode.
LV-CMOS output, Inversion of DIRI in normal operation. Can be used to drive the DIRI
No connect if not used.
signal of the deserializer where the interface needs to be turned around.
Power supply for parallel I/O. (All VDDP pins must be connected to VDDP)
Power supply for serial I/O.
Power supply for core.
All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 29 & GND PAD must be grounded.
No connect. (Do not connect to GND or VDD)
Note:
1. 0=GND; 1=VDDP
FIN210AC (Serializer DIRI=1) Pin Configurations
27 STROBE
26 CKREF
1
A
B
C
D
E
F
G
DP[4]
2
DP[2]
3
GND
4
CTL_ADJ
5
N/C
6
28 CTL_ADJ
CKREF
DP[6]
DP[5]
DP[1]
N/C
STROBE
/DIRO
29 GND
25 /DIRO
32 DP[3]
31 DP[2]
30 DP[1]
DP[4] 1
CKP
N/C
DP[3]
N/C
CKSO+
CKSO -
24 CKSO+
23 CKSO-
SERIALIZER
GND PAD
22 DSO+
21 DSO-
20 CKSI-
19 CKSI+
18 DIRI
17 VDDS
PLL0 13
GND 11
PLL1 12
S1 14
S0 15
DP[10] 9
VDDA 16
www.fairchildsemi.com
DP[5] 2
DP[6] 3
VDDP 4
CKP 5
DP[7] 6
DP[8] 7
DP[9] 8
GND 10
N/C
DP[7]
VDDP
GND
DSO-
DSO+
DP[8]
DP[9]
GND
VDDS
CKSI+
CKSI-
DP[10]
GND
N/C
VDDA
N/C
DIRI
GND
N/C
PLL1
PLL0
S1
S0
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
32-pin MLP, 5 x 5mm, .5mm pitch (Top View)
(Center pad must be grounded)
Figure 2. FIN210AC (Serializer DIRI=1) Pin Assignments (Top View)
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
2
µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
FIN210AC (Deserializer DIRI=0) Pin Descriptions
Pin Name
DIRI
XTERM
S0
S1
PWS0
PWS1
/ENZ
DP[1:10]
CKP
DSI+
DSI-
CKSI+
CKSI-
CKSO+
CKSO-
CKREF
STROBE
/DIRO
VDDP
VDDS
VDDA
GND
N/C
Description
Control to determine serializer or deserializer configuration.
Control to determine if using internal or external termination
Signals used to define the edge rate of parallel I/O.
Signals used to define the edge rate of parallel I/O.
Configure CKP pulse width.
Configure CKP pulse width.
0 Deserializer
1 Serializer
0 Internal termination used
1 External termination required on CKSI & DSI
See Table 2 Deserializer (DIRI=0) Control Pin.
See Table 2 Deserializer (DIRI=0) Control Pin.
See Table 2 Deserializer (DIRI=0) Control Pin.
See Table 2 Deserializer (DIRI=0) Control Pin.
High-Z or known state outputs during power down
See Table 5 Deserializer (DIRI=0) Control Pin.
LV-CMOS parallel data output. (N/C if not used)
LV-CMOS word clock output or Pixel clock output.
CTL Differential serial input data signals.
DSI+: Positive signal; DSI-: Negative signal.
CTL Differential deserializer input bit clock.
CKSI+: Positive signal; CKSI-: Negative signal.
CTL Differential serializer output bit clock.
No connect unless in “clock pass-through” mode.
CKSO+: Positive signal; CKSO-: Negative signal.
LV-CMOS clock input and PLL reference.
No connect unless in “clock pass-through” mode.
LV-CMOS strobe input for latching data into the serializer.
No connect unless in “clock pass-through” mode.
LV-CMOS Output. Inversion of DIRI in normal operation.
No connect if not used.
Power supply for parallel I/O. (All VDDP pins must be connected to VDDP)
Power supply for serial I/O.
Power supply for core.
All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 28, 29, GND PAD must be grounded.
No connect. BGA: G1, F2; MLP: 10, 11; (Do not connect to GND or VDD)
Note:
2. 0=GND; 1=VDDP
FIN210AC (Deserializer DIRI=0) Pin Configurations
27 STROBE
29 XTRM
26 CKREF
1
A
DP[4]
2
DP[2]
3
XTRM
4
/ENZ
5
N/C
6
31 DP[2]
CKREF
B
DP[6]
DP[5]
DP[1]
N/C
STROBE
/DIRO
25 /DIRO
32 DP[3]
30 DP[1]
28 /ENZ
DP[4] 1
CKP
N/C
DP[3]
N/C
CKSO+
CKSO-
24 CKSO+
23 CKSO-
DESERIALIZER
GND PAD
22 DSI-
21 DSI+
20 CKSI-
19 CKSI+
18 DIRI
17 VDDS
PWS0 13
N/C 11
PWS1 12
S1 14
S0 15
DP[10] 9
VDDA 16
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C
DP[5] 2
DP[6] 3
VDDP 4
CKP 5
DP[7] 6
DP[8] 7
DP[9] 8
N/C 10
D
N/C
DP[7]
VDDP
GND
DSI+
DSI-
E
DP[8]
DP[9]
GND
VDDS
CKSI+
CKSI-
F
DP[10]
N/C
N/C
VDDA
N/C
DIRI
G
N/C
N/C
PWS1
PWS0
S1
S0
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
32-pin MLP, 5mm x 5mm, .5mm pitch (Top View)
(Center pad must be grounded)
Figure 3. FIN210AC (Deserializer DIRI=0) Pin Assignments (Top View)
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
3
µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
System Control Pin
Table 1.
Serializer (DIRI=1) Control Pin
Function
Conditions
CKREF
STROBE
Slow Frequencies
Normal operation
Supports spread spectrum on CKREF
With a fixed CKREF input; STROBE
can be 1/2 the speed
With a fixed CKREF input; STROBE
can be 1/3 the speed
Normal operation
Supports spread spectrum on CKREF
With a fixed CKREF input; STROBE
can be 1/2 the speed
With a fixed CKREF input; STROBE
can be 1/3 the speed
Normal operation
Supports spread spectrum on CKREF
With a fixed CKREF input; STROBE
can be 1/2 the speed
With a fixed CKREF input; STROBE
can be 1/3 the speed
5MHz to 15MHz
5MHz to 14.2MHz
5MHz to 15MHz
5MHz to 15MHz
≤
CKREF (Up to 15MHz)
≤
CKREF (Up to 14.2MHz)
≤
CKREF / 2 (Up to 7.5MHz)
≤
CKREF / 3 (Up to 5MHz)
1
0.947
2
3
1
0
0
1
0
0
1
1
0
0
0
0
1
1
1
1
PLL
Multiplier
PLL0
Control Pin
PLL1
S0
S1
Medium Frequencies
10MHz to 30MHz
10MHz to 28.4MHz
10MHz to 30MHz
10MHz to 30MHz
≤
CKREF (Up to 30MHz)
≤
CKREF (Up to 28.4MHz)
≤
CKREF / 2 (Up to 15MHz)
≤
CKREF / 3 (Up to 10MHz)
Fast Frequencies
18MHz to 48MHz
18MHz to 45.4MHz
18MHz to 48MHz
18MHz to 48MHz
Power-Down
≤
CKREF (Up to 48MHz)
≤
CKREF (Up to 45.4MHz)
≤
CKREF / 2 (Up to 24MHz)
≤
CKREF / 3 (Up to 16MHz)
1
0.947
2
3
1
0
0
1
X
0
0
1
1
X
1
1
1
1
0
0
0
0
0
0
1
0.947
2
3
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
Table 2.
Deserializer (DIRI=0) PWS Control Pins (Pulse Width Examples)
CKP Pulse Width Low Time
CKREF=19.2
MHz
CKREF=26
MHz
CKREF=48
MHz
Reference
PLL
Multiplier
(Serializer)
Pwidth
Multiplier
Control Pin
PWS0
PWS1
CKP to STROBE
Serializer PLL Multiplier = 3
Non-Inverted
Inverted
Non-Inverted
Non-Inverted
Non-Inverted
Inverted
Non-Inverted
Non-Inverted
Non-Inverted
Inverted
Non-Inverted
Non-Inverted
78.1ns
78.1ns
156.3ns
208.3ns
52.1ns
52.1ns
104.2ns
138.9ns
26ns
26ns
52.1ns
69.4ns
Power-Down
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
4
57.7ns
57.7ns
115.4ns
153.8ns
38.5ns
38.5ns
76.9ns
102.6ns
19.2ns
19.2ns
38.5ns
51.3ns
31.2ns
31.2ns
62.5ns
83.3ns
20.8ns
20.8ns
41.7ns
55.6ns
10.4ns
10.4ns
20.8ns
27.8ns
3
3
3
3
2
2
2
2
1
1
1
1
X
6
6
12
16
6
6
12
16
6
6
12
16
X
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
www.fairchildsemi.com
Serializer PLL Multiplier = 2
Serializer PLL Multiplier = 1
µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Table 3.
Deserializer S0 & S1 Control Pins (Note: All edge rates are typical values)
LVCMOS Output Edge Rates
S0
0
1
1
0
S1
1
1
0
0
Slow Edge Rates
Medium Edge Rates
Fast Edge Rates
Power Down
~7 - 8ns (C
L
= 8pF)
~4 - 5ns (C
L
= 8pF)
~2 - 3ns (C
L
= 8pF)
Pulse Width Calculations
CKP Pulse Width Low Time=(PLL Multiplier • Pwidth Multiplier) / (CKREF•12)
Example:
CKREF=26MHz
;
PLL Multiplier=1; Pwidth Multiplier=6
CKP Pulse width=(1 • 6) / (26MHz • 12)=19.2ns
(2)
(1)
CKREF = Strobe 50% Duty Cycle
If CKREF = Strobe the below control states will provide a ~ 50% duty cycle pulse width output on CKP
Table 4.
CKREF = Strobe 50% Duty Cycle
Serializer
PLL0
1
PLL1
0
PWS0
0
Deserializer
PWS1
0
Power-Down States
When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN210AC resets and powers down. The
power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all
internal digital logic. Table 5 indicates the state of the input states and output buffers in Power-Down mode.
Table 5.
Power-Down
DIRI=1 (Serializer)
Inputs Disabled
HIGH
Input Disabled
Input Disabled
0
Signal Pins
DP[1:10]
CKP
STROBE
CKREF
/DIRO
DIRI=0 (Deserializer)
/ENZ = 0
Outputs High-Z
High-Z
Input Disabled
Input Disabled
1
DIRI=0 (Deserializer)
/ENZ = 1
Outputs Low
High
Input Disabled
Input Disabled
1
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
5
www.fairchildsemi.com
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