MC56F8345/D
Rev. 3.0 10/2003
56F8345
Preliminary Technical Data
56F8345 16-bit Hybrid Controller
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 128KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Two 6-channel PWM Modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
RSTO
RESET
6
3
4
6
3
4
4
4
5
4
4
PWM Outputs
Current Sense Inputs
or GPIOC
Fault Inputs
PWM Outputs
Current Sense Inputs
or GPIOD
Fault Inputs
Program Controller
and Hardware
Looping Unit
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Two Quadrature Decoders
FlexCAN Module
Optional On-Chip Regulator
Two Serial Communication Interfaces (SCIs)
Up to two Serial Peripheral Interface (SPIs)
Up to four General Purpose Quad Timers
Computer Operating Properly (COP)/Watchdog
JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
V
PP
2
V
CAP
4
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
5
JTAG/
EOnCE
Port
V
DDA
2
V
SSA
PWMA
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
PWMB
Data ALU
16 x 16 + 36 Æ 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
AD0
ADCA
AD1
VREF
PAB
PDB
CDBR
CDBW
Memory
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
AD0
AD1
Temp_Sense
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC
Quad Timer
C or GPIOE
Quad Timer
D or GPIOE
FlexCAN
System Bus
Control
External Bus
Interface Unit
ADCB
*
External
Address Bus
Switch
6
5
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
*
External
Data
Bus Switch
4
D7-10 or GPIOF0-3
*
Bus
Control
6
GPIOD0-5 or CS2-7
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
2
4
Decoding
Peripherals
Clock
resets
PLL
*
EMI not functional in
this package; use as
GPIO pins
2
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Interrupt
Watchdog Controller
System
O
Integration
R
Module
CLKO
P
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA IRQB
CLKMODE
56F8345 Block Diagram - 128 LQFP
© Motorola, Inc., 2003. All rights reserved.
56F8345 Data Sheet Table of Contents
Part 1: Overview. . . . . . . . . . . . . . . . . . . . . 3
1.1. 56F8345 Features . . . . . . . . . . . . . . . . . .
1.2. 56F8345 Description . . . . . . . . . . . . . . . .
1.3. State of the Art Development
Environment . . . . . . . . . . . . . . .
1.4. Architecture Block Diagram . . . . . . . . . . .
1.5. Product Documentation . . . . . . . . . . . . . .
1.6. Data Sheet Conventions . . . . . . . . . . . . .
3
4
5
5
8
9
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . 102
8.2. Configuration . . . . . . . . . . . . . . . . . . . . 102
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . 106
Part 9: Joint Test Action Group (JTAG) 106
9.1. 56F8345 Information . . . . . . . . . . . . . . 106
Part 2: Signal/Connection Descriptions 10
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 10
2.2. 56F8345 Signal Pins . . . . . . . . . . . . . . . 12
Part 10: Specifications . . . . . . . . . . . . . 106
10.1. General Characteristics. . . . . . . . . . . 106
10.2. DC Electrical Characteristics . . . . . . . 111
10.3. AC Electrical Characteristics . . . . . . . 114
10.4. Flash Memory Characteristics . . . . . . 115
10.5. External Clock Operation Timing . . . . 116
10.6. Phase Locked Loop Timing. . . . . . . . 116
10.7. Crystal Oscillator Timing . . . . . . . . . . 117
10.8. Reset, Stop, Wait, Mode Select,
and Interrupt Timing 117
10.9. Serial Peripheral Interface
(SPI) Timing . . . . . . . . . . . . . 119
10.10. Quad Timer Timing . . . . . . . . . . . . . 122
10.11. Quadrature Decoder Timing . . . . . . . 123
10.12. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . 124
10.13. Controller Area Network
(CAN) Timing . . . . . . . . . . . . . 124
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . 125
10.15. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . 127
10.16. Equivalent Circuit for ADC Inputs . . . 128
10.17. Power Consumption . . . . . . . . . . . . 128
Part 3: On-Chip Clock Synthesis (OCCS) 27
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 27
3.2. External Clock Operation . . . . . . . . . . . 27
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . 29
Part 4: Memory Map . . . . . . . . . . . . . . . . 29
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers .
29
30
31
34
34
36
37
Part 5: Interrupt Controller (ITCN) . . . . . 57
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . .
57
57
57
59
59
60
83
Part 11: Packaging . . . . . . . . . . . . . . . . . 130
11.1. Package and Pin-Out Information
56F8345 . . . . . . . . . . . . . . . . 130
Part 6: System Integration Module (SIM) 84
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . .
Operating Mode Register . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . .
Clock Generation Overview . . . . . . . . .
Power-Down Modes Overview . . . . . . .
Stop and Wait Mode Disable Function . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . .
84
84
85
85
86
97
97
98
98
Part 12: Design Considerations . . . . . . 133
12.1. Thermal Design Considerations . . . . . 133
12.2. Electrical Design Considerations . . . . 134
12.3. Power Distribution and I/O Ring
Implementation 135
Part 13: Ordering Information . . . . . . . 135
Part 7: Security Features . . . . . . . . . . . . 99
7.1. Operation with Security Enabled . . . . . . 99
7.2. Flash Access Blocking Mechanisms . . . 99
Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.
2
56F8345 Technical Data
Preliminary
MOTOROLA
56F8345 Features
Part 1 Overview
1.1 56F8345 Features
1.1.1
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Digital Signal Processing Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
As many as 60 Million Instructions Per Second (MIPS) at 60 MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
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Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection feature
On-chip memory including a low-cost, high-volume Flash solution
— 128KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 8KB of Data RAM
— 8KB of Boot Flash
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EEPROM emulation capability
1.1.3
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Peripheral Circuits for 56F8345
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
four Fault inputs, fault-tolerant design with dead time insertion; supports both center- and
edge-aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer
C, channels 2 and 3
Two four-input Quadrature Decoders or two additional Quad Timers
Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the
on-chip temperature
Four dedicated General Purpose Quad Timers totaling six dedicated pins: Timer C with two pins
and Timer D with four pins
Optional On-Chip Regulator
56F8345 Technical Data
Preliminary
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MOTOROLA
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FlexCAN (CAN Version 2.0 B-compliant) Module with 2-pin port for transmit and receive
Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional
GPIO lines). SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B
Computer-Operating Properly (COP)/Watchdog timer
Two dedicated external interrupt pins
49 General Purpose I/O (GPIO) pins; 21 pins dedicated to GPIO
External reset input pin for hardware reset
External reset output pin for system reset
Integrated low-voltage interrupt module
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,
real-time debugging
Software-programmable, Phase Lock Loop-based frequency synthesizer for the core clock
1.1.4
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Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 56F8345 Description
The 56F8345 is a member of the 56800E core-based family of hybrid controllers. It combines, on a single
chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility,
and compact program code, the 56F8345 is well-suited for many applications. The 56F8345 includes many
peripherals that are especially useful for applications such as motion control, smart appliances, steppers,
encoders, tachometers, limit switches, power supply and control, automotive control, engine management,
noise suppression, remote utility metering, industrial control for power, lighting, and automation.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The
instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F8345 supports program execution from internal memories. Two data operands can be accessed from
the on-chip data RAM per instruction cycle. The 56F8345 also provides two external dedicated interrupt
lines and up to 49 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F8345 controller includes 128KB of Program Flash and 8KB of Data Flash (each programmable
through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM.
A total of 8KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable software
routines that can be used to program the main Program and Data Flash memory areas. Both Program and
Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is
1K bytes. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk
or page erased.
4
56F8345 Technical Data
Preliminary
MOTOROLA
State of the Art Development Environment
A key application-specific feature of the 56F8345 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
output pairs (each module is also capable of supporting six independent PWM functions for a total of 12
PWM outputs) to enhance motor control functionality. Complementary operation permits programmable
dead time insertion, distortion correction via current sensing by software, and separate top and bottom
output polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC
and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors),
and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with
sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once
protection feature for key parameters is also included. A patented PWM waveform distortion correction
circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral
reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to synchronize
the analog-to-digital converters through two channels of Quad Timer C.
The 56F8345 incorporates two Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This hybrid controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and four Quad Timers. Any of
these interfaces can be used as General-Purpose Input/Outputs (GPIOs) if that function is not required. A
Flex Controller Area Network interface (CAN Version 2.0 B-compliant) and an internal interrupt controller
are also a part of the 56F8345.
1.3 State of the Art Development Environment
Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools
solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8345 architecture is shown in
Figure 1-1
and
Figure 1-2. Figure 1-1
illustrates how the 56800E
system buses communicate with internal memories and the IP Bus Bridge.
Table 1-1
lists the internal buses
in the 56800E architecture and provides a brief description of their function.
Figure 1-2
shows the
peripherals and control blocks connected to the IP Bus Bridge. The figures do not show the on-board
regulator and power and ground signals. They also do not show the multiplexing between peripherals or the
dedicated GPIOs. Please see
Section 2, Signal/Connection Descriptions,
to see which signals are
multiplexed with those of other peripherals.
Also shown in
Figure 1-2
are connections between the PWM, Timer C and ADC blocks. These connections
allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The Timer C channel
indicated can generate periodic start (SYNC) signals to the ADC to start its conversions. In another
operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer C input
channel as indicated. The timer can then be used to introduce a controllable delay before generating its
output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the
56F8300 Peripheral User’s Manual
for clarification on the operation of all three of these peripherals.
MOTOROLA
56F8345 Technical Data
Preliminary
5
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