MC56F8357/D
Rev. 1.0, 10/2003
56F8357
Preliminary Technical Data
56F8357 16-bit Digital Signal Processor
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 4MB of off-chip program and 32MB
of data memory
• Chip Select Logic for glueless interface to ROM
and SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB Boot Flash
• Two 6-channel PWM Modules
• Four 4-channel, 12-bit ADCs
RSTO
EMI_MODE
EXTBOOT
5
JTAG/
EOnCE
Port
V
PP
2
V
CAP*
4
OCR_DIS
V
DD
V
SS
7
6
Digital Reg
V
DDA
2
Analog Reg
V
SSA
RESET
6
3
4
6
3
4
4
4
5
4
4
• Temperature Sensor
• Two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN Module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four General Purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 76 GPIO lines
• 160-pin LQFP Package
* Configuration
shown for on-chip
2.5V regulator
PWM Outputs
PWMA
Current Sense Inputs/GPIOC
Fault Inputs
PWM Outputs
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Current Sense Inputs/GPIOD
Fault Inputs
A/D0
A/D1
VREF
A/D0
A/D1
Temp_Sense
Quadrature
Decoder 0/
Quad
Timer A/
GPIOC
Quadrature
Decoder 1/
Quad
Timer B/
SPI1/GPIOC
Quad
Timer C/
GPIOE
Quad
Timer D/
GPIOE
FlexCAN
SPI0 or
GPIOE
4
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 Æ 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
ADCA
PAB
PDB
CDBR
CDBW
Memory
ADCB
Program Memory
128K x 16 Flash
2K x 16 RAM
8K x 16 Boot
Flash
Data Memory
4K x 16 Flash
8K x 16 RAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
External
Address Bus
Switch
6
2
8
4
1
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
**See Table 2-2
for explanation
External Bus
Interface Unit
System Bus
Control
3
7
8
4
External Data
Bus Switch
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
Bus Control
6
2
Decoding
Peripherals
Clock resets
PLL
4
2
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
P
System
O
Integration
R
Module
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA
IRQB
CLKO
CLKMODE
56F8357 Block Diagram
© Motorola, Inc., 2003. All rights reserved.
56F8357 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . 3
1.1. 56F8357 Features . . . . . . . . . . . . . . . . . .
1.2. 56F8357 Description . . . . . . . . . . . . . . . .
1.3. Award-Winning Development
Environment . . . . . . . . . . . . . . .
1.4. Architecture Block Diagram . . . . . . . . . . .
1.5. Product Documentation . . . . . . . . . . . . . .
1.6. Data Sheet Conventions . . . . . . . . . . . . .
3
4
5
5
8
9
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . 113
8.2. Configuration. . . . . . . . . . . . . . . . . . . . 113
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . 117
Part 9: Joint Test Action Group (JTAG) 117
9.1. 56F8357 Information . . . . . . . . . . . . . . 117
Part 2: Signal/Connection Descriptions 10
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 10
2.2. 56F8357 Signal Pins . . . . . . . . . . . . . . . 12
Part 10: Specifications . . . . . . . . . . . . . 118
10.1. General Characteristics . . . . . . . . . . . 118
10.2. DC Electrical Characteristics . . . . . . . 123
10.3. AC Electrical Characteristics . . . . . . . 127
10.4. Flash Memory Characteristics . . . . . . 127
10.5. External Clock Operation Timing . . . . 128
10.6. Phase Locked Loop Timing . . . . . . . . 128
10.7. Crystal Oscillator Timing . . . . . . . . . . 129
10.8. External Memory Interface Timing . . . 129
10.9. Reset, Stop, Wait, Mode Select,
and Interrupt Timing . . . . . . . 132
10.10. Serial Peripheral Interface
(SPI) Timing . . . . . . . . . . . . . . 134
10.11. Quad Timer Timing . . . . . . . . . . . . . 138
10.12. Quadrature Decoder Timing . . . . . . . 138
10.13. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . 139
10.14. Controller Area Network
(CAN) Timing . . . . . . . . . . . . . 140
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . 140
10.16. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . 142
10.17. Equivalent Circuit for ADC Inputs . . . 143
10.18. Power Consumption . . . . . . . . . . . . 143
Part 3: On-Chip Clock Synthesis (OCCS) 31
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 31
3.2. External Clock Operation . . . . . . . . . . . 31
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . 33
Part 4: Memory Operating Modes (MEM) 33
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers .
33
34
35
38
38
39
40
Part 5: Interrupt Controller (ITCN) . . . . . 66
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . .
66
66
66
68
68
69
93
Part 11: Packaging . . . . . . . . . . . . . . . . . 145
11.1. Package and Pin-Out Information
56F8357 . . . . . . . . . . . . . . . . 145
Part 6: System Integration
Module (SIM) . . . . . . . . . . . . . . . . . . . . . . 94
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Overview . . . . . . . . . . . . . . . . . . . . . . . . 94
Features . . . . . . . . . . . . . . . . . . . . . . . . 94
Operating Modes . . . . . . . . . . . . . . . . . . 94
Operation Mode Register . . . . . . . . . . . . 95
Register Descriptions . . . . . . . . . . . . . . . 96
Clock Generation Overview . . . . . . . . 108
Power Down Modes Overview . . . . . . 108
Stop and Wait Mode Disable Function 109
Resets . . . . . . . . . . . . . . . . . . . . . . . . . 109
Part 12: Design Considerations . . . . . . 149
12.1. Thermal Design Considerations . . . . 149
12.2. Electrical Design Considerations . . . . 150
12.3. Power Distribution and I/O Ring
Implementation
151
Part 13: Ordering Information . . . . . . . 151
Part 7: Security Features. . . . . . . . . . . . 110
7.1. Operation with Security Enabled . . . . . 110
7.2. Flash Access Blocking Mechanisms . . 110
Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.
2
56F8357 Technical Data
Preliminary
MOTOROLA
56F8357 Features
Part 1 Overview
1.1 56F8357 Features
1.1.1
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Digital Signal Processing Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
As many as 60 Million Instructions Per Second (MIPS) at 60 MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
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Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection feature
On-chip memory including a low-cost, high-volume flash solution
— 256KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 16KB of Data RAM
— 16KB of Boot Flash
•
Off-chip memory expansion capabilities provide a simple method for interfacing additional external
memory and/or peripheral devices
— Access up to 4MB of external program memory or 32MB of external data memory
— Chip select logic for glueless interface to ROM and SRAM
EEPROM emulation capability
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1.1.3
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Peripheral Circuits for 56F8357
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
four Fault inputs, fault-tolerant design with dead time insertion, supports both center-aligned and
edge-aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer
C, channels 2 and 3
56F8357 Technical Data
Preliminary
3
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MOTOROLA
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Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the
on-chip temperature
Two four-input Quadrature Decoders or two additional Quad Timers
Four dedicated General Purpose Quad Timers totaling dedicated six pins: Timer C with two pins
and Timer D with four pins
FlexCAN (CAN Version 2.0 B-compliant ) Module with 2-pin port for transmit and receive
Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)
Two Serial Peripheral Interfaces (SPIs) with configurable 4-pin port (or eight additional GPIO
lines). SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B
Computer-Operating Properly (COP) / Watchdog timer
Two dedicated external interrupt pins
Up to 76 General Purpose I/O (GPIO) pins
External reset input pin for hardware reset
External reset output pin for system reset
Integrated Low-Voltage Interrupt Module
JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent
debugging
Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock
1.1.4
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Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 56F8357 Description
The 56F8357 is a member of the 56800E core-based family of hybrid controllers. It combines, on a single
chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility,
and compact program code, the 56F8357 is well-suited for many applications. The 56F8357 includes many
peripherals that are especially useful for applications such as motion control, smart appliances, steppers,
encoders, tachometers, limit switches, power supply and control, automotive control, engine management,
noise suppression, remote utility metering, industrial control for power, lighting, and automation.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The
instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F8357 supports program execution from internal or external memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. The 56F8357 also provides two external
dedicated interrupt lines and up to 76 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
4
56F8357 Technical Data
Preliminary
MOTOROLA
Award-Winning Development Environment
The 56F8357 hybrid controller includes 256KB of Program Flash and 8KB of Data Flash (each
programmable through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM.
A total of 16KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable software
routines that can be used to program the main Program and Data Flash memory areas. Both Program and
Data Flash memories can be independently bulk erased or erased in page sizes. Program Flash page erase
size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either
bulk or page erased.
A key application-specific feature of the 56F8357 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12
PWM outputs) to enhance motor control functionality. Complementary operation permits programmable
dead time insertion, distortion correction via current sensing by software, and separate top and bottom
output polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC
and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors),
and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with
sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once
protection feature for key parameters is also included. A patented PWM waveform distortion correction
circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral
reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to synchronize
the analog-to-digital converters through two channels of Quad Timer C.
The 56F8357 incorporates two Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a timeout value to alarm when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This hybrid controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and four Quad Timers. Any of
these interfaces can be used as General-Purpose Input/Outputs (GPIOs) if that function is not required. A
Flex Controller Area Network interface (CAN Version 2.0 B-compliant) and an internal interrupt controller
are included on the 56F8357.
1.3 Award-Winning Development Environment
Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools
solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8357 architecture is shown in
Figure 1-1
and
Figure 1-2. Figure 1-1
illustrates how the 56800E
system buses communicate with internal memories, the external memory interface and the IP Bus Bridge.
Table 1-1
lists the internal buses in the 56800E architecture and provides a brief description of their
function.
Figure 1-2
shows the peripherals and control blocks connected to the IP Bus Bridge. The figures
do not show the on-board regulator and power and ground signals. They also do not show the multiplexing
between peripherals or the dedicated GPIOs. Please see
Section 2, Signal/Connection Descriptions,
to see
which signals are multiplexed with those of other peripherals.
MOTOROLA
56F8357 Technical Data
Preliminary
5
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