Standard Products
UT69151 SµMMIT
TM
RTE
Product Handbook
June 1999
FEATURES
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Comprehensive MIL-STD-1553 dual redundant Remote
Terminal (RT) with integrated bus transceivers, Memory,
and Memory Management Unit (MMU)
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MIL-STD-1553B, Notice II RT
- Internal command illegalization
- 16-bit read/write time-tag with user-defined resolution
- Subaddress data buffering
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Programmable interrupt architecture with automatic
interrupt logging available
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Autonomous operation
- External initialization bus
- Ideal for low cost remote terminals
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Internal Memory Management Unit (MMU) interfaces host
subsystem to 64Kbit SRAM
- Wait state and zero-wait state configurations
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Built-In Test capability
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Supports IEEE Standard 1149.1 (JTAG)
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Flexible power supply configurations
- +5-volt only operation
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Flexible packaging offering:
- 139-pin pingrid array (PGA)
- 140-lead flatpack
- 132-lead flatpack
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Standard Microcircuit Drawing 5962-98587
MODE
STATUS
JTAG
INTERRUPTS
CHA
TRANSCEIVER
CHA
DATA
SµMMIT
Protocol
Handler
CHB
TRANSCEIVER
CHB
MEMORY
MMU
INTERFACE
CONTROL
Auto-Init Bus
ADDRESS
REMOTE
TERMINAL
ADDRESS
Figure 1. UT69151 SµMMIT RTE Block Diagram
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2.0 R
EMOTE
T
ERMINAL
A
RCHITECTURE
The SµMMIT Remote Terminal (RTE) is an interface device
linking a MIL-STD-1553 serial data bus to a host
microprocessor and/or subsystem. The SµΜΜIT RTE’s MIL-
STD-1553 interface includes encoding/decoding logic, error
detection, command recognition, DMA interface, control/
configuration registers, clock, and reset logic. The following
sections review the architecture and use. Each section supplies
information on the SµΜΜIT RTE’s configuration and
operation.
2.1 Register Descriptions
The following list provides the bit descriptions of the 32 internal
registers that control SµΜΜIT RTE operation. All register bits
are active high and reflect a logic zero condition (0000 hex) after
Master Reset (except those reflecting input pins).
Register
Number
0
1
2
3
4
5
6
7
8
9
10-15
16-31
Name
Control Register
Operational Status Register
Current Command Register
Interrupt Mask Register
Pending Interrupt Register
Interrupt Log List Pointer Register
BIT Word Register
Time-Tag Register
RT Descriptor Pointer Register
1553 Status Word Bits Register
Not Applicable
Illegalization Registers
Register Address
0000 (hex)
0001 (hex)
0002 (hex)
0003 (hex)
0004 (hex)
0005 (hex)
0006 (hex)
0007 (hex)
0008 (hex)
0009 (hex)
000A to 000F (hex)
0010 to 001F (hex)
Note: Reference section 7.1, Table 12 for SµMMIT RTE 8-bit register address numbers.
2.1.1 Control Register (Read/Write) - Register 0
This 16-bit register controls SµΜΜIT RTE configuration. To make changes to the SµΜΜIT RTE and this register, the STEX bit
(Bit 15 of the Control Register) must be logic zero. Note: The user has 5µs after TERACT active to stop execution.
Bit
Number
15
Mnemonic
STEX
Description
Start Execution. Assertion of this bit initiates SµΜΜIT RTE operation. A
Control Register write negating this bit inhibits SµΜΜIT RTE operation. A
remote terminal address parity error prevents SµΜΜIT RTE operation
regardless of the logical state of this bit. If a RT address parity error exists, bit
3 of Register 1 will be set low and bit 2 of Register 1 will be set high.
Start BIT. Assertion of this bit places the SµΜΜIT RTE into the Built-In Test
routine. The BIT test has a fault coverage of 93.4%. If the SµΜΜIT RTE has
been started, the host must halt the device in order to place the SµΜΜIT RTE
into the Built-In Test routine (STEX = 0) (see section 6.0 for additional
information).
Note: If Start BIT (SBIT) and Start Execution (STEX) are both set on one register
write, BIT has priority.
14
SBIT
2
SµMMIT RTE
Bit
Number
13
Mnemonic
Mnemonic
SRST
Description
Description
Software Reset. Assertion of this bit immediately places the SµΜΜIT RTE into
a software reset. The software reset (which takes 5µs to execute), like MRST,
clears all internal logic.
Note: During auto-initialization this bit should not be loaded with a logic one.
SRST will only function after READY is asserted.
Channel A Enable. Setting this bit enables Channel A operation. If negated, the
SµΜΜIT RTE does not recognize commands received over Channel A.
Channel B Enable. Setting this bit enables Channel B operation. If negated, the
SµΜΜIT RTE does not recognize commands received over Channel B.
External Timer Clock Enable. Assertion of this bit to a logic one allows the
external timer clock input to supply stimulus to the internal time-tag counter.
Refer to section 2.1.8 for additional information.
Note: The user can only change the clock frequency before starting the device
(i.e., setting bit 15 of Register 0 to a logic one).
Ping-pong acknowledge made. See section 3, Circular Buffer and Ping-Pong
Operation for additional information.
Circular buffer mode select. See section 3, Circular Buffer and Ping-Pong
Operation for additional information.
Circular buffer mode select. See section 3, Circular Buffer and Ping-Pong
Operation for additional information.
Always set this bit to logical zero.
Always set this bit to logical zero.
Broadcast Enable. Assertion of this bit enables the SµΜΜIT RTE broadcast
option. Negation of this bit enables remote terminal address 31 as a unique
remote terminal address.
Dynamic Bus Control Acceptance. This bit controls the SµΜΜIT RTE’s ability
to accept the dynamic bus control mode code. Assertion of this bit allows the
SµΜΜIT RTE to respond to a dynamic bus control mode code with status word
bit 18 set to a logic one. Negation of this bit prevents the assertion of status word
bit 18 upon reception of the dynamic mode code.
Ping-Pong Enable. Assertion of this bit enables the ping-pong buffer feature of
the SµΜΜIT RTE and disables the message indexing feature. Negation of this
bit disables the ping-pong feature and enables the message indexing feature. See
section 3, Circular Buffer and Ping-Pong Operation for additional information.
Interrupt Log Enable. Assertion of this bit enables the SµΜΜIT interrupt logging
feature. Negation of this bit prevents the logging of interrupts.
Transmit Status Word. Assertion of this bit allows the SµΜΜIT RTE to
automatically execute the TRANSMIT STATUS WORD mode code when
configured for MIL-STD-1553A mode operation. Refer to section 2.9 for
additional information.
12
11
10
CHAEN
CHBEN
ETCE
9
8
7
6
5
4
PPACK
CBSEL1
CBSEL2
N/A
N/A
BCEN
3
DYNBC
2
PPEN
1
0
INTEN
XMTSW
SµMMIT RTE
3
2.1.2 Operational Status Register (Read/Write) - Register 1
This register reflects pertinent status information for the SµΜΜIT RTE and is not reset to 0000 (hex) on MRST. Instead, the register
reflects the actual stimulus applied to input pins RTA(4:0), RTPTY, A/B STD, and LOCK. Assertion of the LOCK input prevents
the modification of the remote terminal address, mode selects, and A or B Standard. In this case, a write to this register’s most
significant nine bits is meaningless. If LOCK is negated, a read of this register reflects the information written into this register’s
most significant nine bits.
Note: To make changes to the SµΜΜIT RTE and this register, the STEX bit (Bit 15 in Register 0) must be logic zero.
Bit
Mnemonic
Description
Number
15
RTA4
Terminal Address Bit 4. This bit is the most significant bit of the remote terminal address.
This bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is
active.
Terminal Address Bit 3. This bit is Bit 3 of the remote terminal address. This bit is latched
on the rising edge of MRST and is a read only bit if the LOCK pin is active.
Terminal Address Bit 2. This bit is Bit 2 of the remote terminal address. This bit is latched
on the rising edge of MRST and is a read only bit if the LOCK pin is active.
Terminal Address Bit 1. This bit is Bit 1 of the remote terminal address. This bit is latched
on the rising edge of MRST and is a read only bit if the LOCK pin is active.
Terminal Address Bit 0. This bit is the least significant bit of the remote terminal address.
This bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is
active.
Terminal Address Parity Bit. This bit is appended to the remote terminal address bus
(RTA(4:0)) to supply odd parity. The SµΜΜIT RTE requires odd parity for proper
operation. This bit is latched on the rising edge of MRST and is a read only bit if the
LOCK pin is active.
Always set this bit to logical zero.
Always set this bit to logical one.
Military Standard 1553A or 1553B Standard. This bit determines whether the SµΜΜIT
RTE will be set to operate under MIL-STD-1553A or B. Assertion of this bit enables the
XMTSW bit (Bit 0 of the Control Register). Negation of this bit automatically allows the
SµΜΜIT RTE to operate under the MIL-STD-1553B protocol. This bit is latched on the
rising edge of MRST and is a read only bit if the LOCK pin is active. See section 2.9 for
further definition.
LOCK Pin. This read-only bit reflects the inverted state of input pin LOCK and is latched
on the rising edge of MRST.
AUTOEN Pin. This read-only bit reflects the inverted state of input pin AUTOEN.
Assertion of this input enables SµΜΜIT RTE auto-initialization.
SSYSF Pin. This read-only bit reflects the inverted state of the input pin SSYSF.
SµΜΜIT RTE Executing. This read-only bit indicates whether the SµΜΜIT RTE is
presently executing or whether it is idle. A logic one indicates that the SµΜΜIT RTE is
executing; logic zero indicates that the SµΜΜIT RTE is idle.
Terminal Address Parity Fail. This bit indicates the observance of a terminal address parity
error. The SµΜΜIT RTE checks for odd parity. This read only bit reflects the parity of
Operational Status Register bits 15-10, and is latched on the rising edge of MRST.
14
13
12
11
RTA3
RTA2
RTA1
RTA0
10
RTPTY
9
8
7
N/A
Logical one
A/B STD
6
5
4
3
LOCK
AUTOEN
SSYSF
EX
2
TAPF
4
SµMMIT RTE
Bit
Number
1
0
Mnemonic
READY
TERACT
Description
READY Pin. This read-only bit reflects the inverted state of the output pin READY and
is cleared on reset.
TERACT Pin. Assertion of this bit indicates that the SµΜΜIT RTE is presently processing
a message. This read only bit reflects the inverted state of output pin TERACT and is
cleared on reset.
Note: Remote Terminal Address and Parity checked on start of execution.
2.1.3 Current Command Register (Read-only) - Register 2
This 16-bit register contains the last valid command processed by the SµΜΜIT RTE.
Bit
Number
15 to 0
Mnemonic
CC15-CC0
Description
Current Command Bits. This register contains the last valid command received by the
SµΜΜIT RTE. This register is valid 13µs after TERACT is negated. (Bit 15 MSB - Bit
0 LSB).
SµMMIT RTE
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