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5962H9654002VXA

产品描述J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, CERAMIC, DFP-16
产品类别逻辑    逻辑   
文件大小489KB,共30页
制造商Cobham PLC
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5962H9654002VXA概述

J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, CERAMIC, DFP-16

5962H9654002VXA规格参数

参数名称属性值
包装说明DFP, FL16,.3
Reach Compliance Codeunknown
ECCN代码3A001.A.1.A
系列AC
JESD-30 代码R-CDFP-F16
JESD-609代码e0
负载电容(CL)50 pF
逻辑集成电路类型J-KBAR FLIP-FLOP
最大频率@ Nom-Sup62000000 Hz
最大I(ol)0.0001 A
位数2
功能数量2
端子数量16
最高工作温度125 °C
最低工作温度-55 °C
输出极性COMPLEMENTARY
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DFP
封装等效代码FL16,.3
封装形状RECTANGULAR
封装形式FLATPACK
电源3.3/5 V
传播延迟(tpd)31 ns
认证状态Qualified
筛选级别MIL-PRF-38535 Class V
座面最大高度2.921 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)3.6 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层TIN LEAD
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
总剂量1M Rad(Si) V
触发器类型POSITIVE EDGE
宽度6.731 mm
Base Number Matches1

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REVISIONS
LTR
A
DESCRIPTION
Changes in accordance with NOR 5962-R143-97.
Incorporate Revision A. Update boilerplate to MIL-PRF-38535 requirements. –
LTG
Add appendix A. – LTG
Add device types 02 and 03. Delete RHA level “H” for device type 01. Add
test circuit to figure 4. Add figure B-1 to appendix A. Update boilerplate and
editorial changes throughout. - LTG
Make corrections for pin numbers 6 and 7 in figure 1, terminal connections.
Editorial changes throughout. - LTG
Correct radiation features in section 1.5 and add footnote 8/. Correct footnotes
2/ and 7/ in Table IA. Correct paragraph 4.4.4.1. Correct SEP test limits in the
table IB. Update boilerplate paragraphs to current MIL-PRF-38535
requirements. - MAA
Make corrections to table IA, output voltage tests V
OH
and V
OL
, change
condition V
IN
- jak
DATE (YR-MO-DA)
96-12-10
APPROVED
Monica L. Poelking
B
C
01-09-04
02-01-31
Thomas M. Hess
Thomas M. Hess
D
04-05-26
Thomas M. Hess
E
05-12-06
Thomas M. Hess
F
09-09-09
Thomas M. Hess
G
11-01-26
Thomas M. Hess
H
Add footnote 5 to figure 4. Add equivalent circuit to figure 4 - jak
12-07-09
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
H
15
H
16
H
17
H
18
REV
SHEET
PREPARED BY
Thanh V. Nguyen
H
19
H
20
H
21
H
1
H
22
H
2
H
23
H
3
H
24
H
4
H
25
H
5
H
26
H
6
H
27
H
7
H
28
H
8
H
9
H
10
H
11
H
12
H
13
H
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
CHECKED BY
Thanh V. Nguyen
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
96-04-12
REVISION LEVEL
MICROCIRCUIT, DIGITAL, ADVANCED CMOS,
RADIATION HARDENED, DUAL J-
K
FLIP-FLOP
WITH CLEAR AND PRESET, MONOLITHIC
SILICON
SIZE
CAGE CODE
H
AMSC N/A
DSCC FORM 2233
APR 97
.
A
67268
5962-96540
SHEET 1 OF 28
5962-E395-12

 
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