A5984
DMOS Microstepping Driver with Translator
and Overcurrent Protection
FEATURES AND BENEFITS
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Drop-in replacement for A4984
Proprietary Adaptive Percent Fast Decay option
Low R
DS(on)
outputs
Single supply
Microstepping up to 32 microsteps per full step
Full torque step modes
Short-to-ground protection
Shorted load protection
Short-to-battery protection
Fault output
Low current Sleep mode, < 10 µA
No smoke no fire (NSNF) compliance (ET package)
Thin profile QFN and TSSOP packages
Thermal shutdown circuitry
Synchronous rectification for low power dissipation
Internal UVLO
Crossover-current protection
DESCRIPTION
The A5984 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors from full-step up to 1/32 step modes.
Step modes are selectable by MSx logic inputs. It has an output
drive capacity of up to 40 V and ±2 A.
A5984 introduces a proprietary Adaptive Percent Fast Decay
(APFD) algorithm to optimize the current waveform over a
wide range of stepper speeds and stepper motor characteristics.
APFD adjusts on-the-fly the amount of fast decay during a
PWM cycle to keep current ripple at a low level over the
various operating conditions. This adaptive feature improves
performance of the system resulting in reduced audible motor
noise, reduced vibration, and increased step accuracy.
The translator is the key to the easy implementation of the
A5984. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A5984 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
The ET package meets customer requirements for no smoke
no fire (NSNF) designs by adding no-connect pins between
critical output, sense, and supply pins. So, in the case of a
pin-to-adjacent-pin short, the device does not cause smoke
or fire. Additionally, the device does not cause smoke or fire
when any pin is shorted to ground or left open.
Continued on the next page…
APPLICATIONS
• Video Security Cameras
• Printers
• Scanners
• Robotics
• ATM
• POS
5V
5 kΩ
SLEEP
STEP
Microcontroller or
Controller Logic
MS1
MS2
MS3
DIR
ENABLE
5V
5 kΩ
RESET
0.1 µF
0.1 µF
ROSC
CP1
CP2
VCP
VBB1
VBB2
OUT1A
100 µF
A5984
OUT1B
SENSE1
OUT2A
OUT2B
GND
PAD
SENSE2
VREF
nFAULT
Typical Application Diagram
5984-DS, Rev. 2
January 3, 2017
A5984
PACKAGES:
24-contact QFN
with exposed thermal pad
4 mm × 4 mm × 0.75 mm
(ES package)
32-contact QFN
with exposed thermal pad
5 mm × 5 mm × 0.90 mm
(ET package)
DMOS Microstepping Driver with Translator
and Overcurrent Protection
DESCRIPTION (continued)
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation. Internal circuit
protection includes: thermal shutdown with hysteresis, undervoltage
lockout (UVLO), and crossover-current protection. Special power-on
sequencing is not required.
The A5984 is supplied in three surface mount packages: two QFN
packages, the 4 mm × 4 mm, 0.75 mm nominal overall height ES
package, and the 5 mm × 5 mm × 0.90 mm ET package. The LP
package is a 24-pin TSSOP. All three packages have exposed pads
for enhanced thermal dissipation, and are lead (Pb) free (suffix –T),
with 100% matte-tin-plated leadframes.
24-pin TSSOP
with exposed thermal pad
(LP Package)
SPECIFICATIONS
SELECTION GUIDE
Part Number
A5984GESTR-T
A5984GETTR-T*
A5984GLPTR-T
Package
24-pin QFN with exposed thermal pad
32-pin QFN with exposed thermal pad
24-pin TSSOP with exposed thermal pad
Packing
1500 pieces per 7-in. reel
1500 pieces per 7-in. reel
4000 pieces per 13-in. reel
* Contact marketing for availability.
ABSOLUTE MAXIMUM RATINGS
Characteristic
Load Supply Voltage
Output Current
Logic Input Voltage
Motor Outputs Voltage
Sense Voltage
Reference Voltage
Operating Ambient Temperature
Maximum Junction
Storage Temperature
V
SENSE
V
REF
T
A
T
J
(max)
T
stg
Range G
Symbol
V
BB
I
OUT
V
IN
Notes
Rating
40
±2
–0.3 to 6
–2.0 to V
BB
+ 2 V
–0.5 to 0.5
5.5
–40 to 105
150
–55 to 150
Units
V
A
V
V
V
V
°C
°C
°C
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A5984
DMOS Microstepping Driver with Translator
and Overcurrent Protection
Specifications
Functional Description
Functional Block Diagram
Pinout Diagrams and Terminal List Table
Electrical Characteristics
Thermal Characteristics
Logic Interface
2
4
5
6
7
8
Table of Contents
Protection Functions
Fault Output (nFAULT)
Thermal or Undervoltage Fault Shutdown
Overcurrent Protection
Layout
Pin Circuit Diagrams
Phase Current Diagrams
Full Step (100% Torque)
Half Step (100% Torque)
Sixteenth Step
Thirty-Secondth Step
Full Step (Modified)
Half Step (Modified)
Eighth Step
Quarter Step
Stepping Phase Tables
Full Torque Modes
Common Modes
13
13
13
13
Application Information
14
14
15
16
16
16
17
17
18
18
19
19
20
20
21
Device Operation
Stepping Current Control
100 Percent Torque Operation
Microstep Select (MSx)
¯¯¯¯¯
Reset Input (¯ ¯ ¯ ¯ ¯ )
RESET
Step Input (STEP)
Direction Input (DIR)
Internal PWM Current Control
Blanking
ROSC
Charge Pump (CP1 and CP2)
¯ ¯ ¯ ¯¯ ¯
Enable Input ( ¯ ¯ ¯ ¯ ¯ ¯ )
ENABLE
¯L E E P
¯¯¯¯
Sleep Mode ( S ¯ ¯ ¯ ¯ )
Synchronous Rectification
9
9
9
9
9
12
12
12
12
12
12
12
13
13
9
Package Outline Drawings
25
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A5984
DMOS Microstepping Driver with Translator
and Overcurrent Protection
0.1 µF
ROSC
CP1
CP2
Internal
Regulator
OSC
Charge
Pump
VCP
0.1 µF
REF
DMOS Full Bridge
VBB1
DAC
OUT1A
OUT1B
STEP
DIR
RESET
MS1
100 k
MS2
100 k
MS3
100 k
ENABLE
SLEEP
5V
V
REF
nFAULT
GND
DAC
Translator
PWM Latch
Blanking
Mixed Decay
OCP
Gate
Drive
SENSE1
DMOS Full Bridge
VBB2
R
S1
Control
Logic
OCP
OUT2A
OUT2B
PWM Latch
Blanking
Mixed Decay
SENSE2
Fault
R
S2
PAD
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A5984
DMOS Microstepping Driver with Translator
and Overcurrent Protection
Pinout Diagrams and Terminal List Table
23 SENSE2
20 SENSE1
32 SENSE2
31 NC
30 OUT2A
25 SENSE1
22 OUT2A
21 OUT1A
29 NC
28 NC
27 OUT1A
26 NC
24 VBB2
19 VBB1
CP1 1
CP2 2
VCP 3
nFAULT 4
MS1 5
MS2 6
RESET 7
ROSC 8
SLEEP 9
MS3 10
STEP 11
REF 12
PAD
24 GND
23 ENABLE
22 OUT2B
21 VBB2
20 SENSE2
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
15 OUT1B
14 DIR
13 GND
OUT2B
ENABLE
GND
CP1
CP2
VCP
1
2
3
4
5
6
RESET 10
SLEEP 12
ROSC 11
PAD
18 OUT1B
17 DIR
16 GND
15 REF
14 STEP
13 MS3
OUT2B
NC
VBB2
NC
ENABLE
GND
CP1
CP2
1
2
3
4
5
6
7
8
PAD
24
23
22
21
20
19
18
OUT1B
NC
VBB1
NC
DIR
GND
REF
17 STEP
MS3 16
ES Package Pinouts
Terminal List Table
Name
CP1
CP2
DIR
¯ ¯ ¯ ¯ ¯¯
¯ ¯ ¯ ¯¯ ¯
ENABLE
nFAULT
GND
MS1
MS2
MS3
NC
OUT1A
OUT1B
OUT2A
OUT2B
REF
¯ ¯¯¯¯
¯ ¯ ¯ ¯¯
RESET
ROSC
SENSE1
SENSE2
¯ ¯¯ ¯ ¯
¯¯ ¯ ¯ ¯
SLEEP
STEP
VBB1
VBB2
VCP
PAD
Number
ES
4
5
17
2
7
3, 16
8
9
13
–
21
18
22
1
15
10
11
20
23
12
14
19
24
6
–
ET*
7
8
20
5
10
6, 19
11
12
16
2, 4, 21, 23,
26, 28, 29, 31
27
24
30
1
18
13
14
25
32
15
17
22
3
9
–
LP
1
2
14
23
4
13, 24
5
6
10
–
18
15
19
22
12
7
8
17
20
9
11
16
21
3
–
ET Package Pinouts
VCP 9
nFAULT 10
MS1 11
MS2 12
RESET 13
ROSC 14
SLEEP 15
nFAULT 7
8
MS1
MS2
9
LP Package Pinouts
Description
Charge pump capacitor terminal
Charge pump capacitor terminal
Logic input
Logic input
Fault output, active low
Ground
Logic input
Logic input
Logic input
No connection
DMOS Full Bridge 1 Output A
DMOS Full Bridge 1 Output B
DMOS Full Bridge 2 Output A
DMOS Full Bridge 2 Output B
G
m
reference voltage input
Logic input
Timing set
Sense resistor terminal for Bridge 1
Sense resistor terminal for Bridge 2
Logic input
Logic input
Load supply
Load supply
Reservoir capacitor terminal
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
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