DATA SHEET
SKY12343-364LF: 0.01 – 4.0 GHz Seven-Bit Digital
Attenuator with Serial and Parallel Drivers
Applications
•
Cellular and 3G infrastructure
•
WiMAX, LTE, 4G infrastructure
Features
•
Broadband operation: 0.01 to 4.0 GHz
•
Attenuation range: 31.75 dB with 0.25 dB LSB
•
TTL/CMOS-compatible serial, parallel, or latched parallel control
interface
•
Single supply voltage: +3.3 or +5 V
•
Small, QFN (32-pin, 5 x 5 mm) Pb-free package (MSL1, 260
°C
per JEDEC J-STD-020)
Figure 1. SKY12343-364LF Block Diagram
Description
The SKY12343-364LF is a GaAs broadband seven-bit pHEMT
digital attenuator with a 0.25 dB Least Significant Bit (LSB). The
programming logic levels are TTL/CMOS-compatible with both a
dual mode serial controller and an integrated Serial Peripheral
Interface (SPI) controller.
The SKY12343-364LF attenuator features low insertion loss,
excellent attenuation accuracy, a 31.75 dB attenuation range, and
high linearity performance. The device is an ideal choice for a
wide variety of 3G and 4G cellular infrastructure applications.
A functional block diagram is shown in Figure 1. The pin
configuration and package are shown in Figure 2. Signal pin
assignments and functional pin descriptions are provided in
Table 1.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201355C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 7, 2012
1
DATA SHEET • SKY12343-364LF SEVEN-BIT DIGITAL ATTENUATOR
Figure 2. SKY12343-364LF Pinout – 32-Pin QFN
(Top View)
Table 1. SKY12343-364LF Signal Descriptions
Pin #
1
2
3
4
5
6
7
N/C
VDD
P/S
A0
N/C
N/C
RF1
Name
Description
No connection (Note 1)
DC power supply
Serial or parallel operation select. Logic low
enables parallel mode.
Address bit A0
No connection (Note 1)
No connection (Note 1)
RF input/output to digital attenuator
Pin #
17
18
19
20
21
22
23
N/C
RF2
N/C
N/C
A2
A1
LATCH_ENABLE
Name
Description
No connection (Note 1)
RF input/output to digital attenuator
No connection (Note 1)
No connection (Note 1)
Address bit A2
Address bit A1
On rising edge of pulse, shifts the most
recent clocked-in data and address bits to
set the attenuation state. In parallel mode, if
this signal is logic high, changes to the V1
through V7 signals occur directly. If this
signal is logic low, the attenuator does not
change states until this signal is raised.
Clock input
Serial data input
Parallel attenuation control input
Parallel attenuation control input
Parallel attenuation control input
Parallel attenuation control input
Parallel attenuation control input
Parallel attenuation control input
Parallel attenuation control input
8
9
10
11
12
13
14
15
16
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
No connection (Note 1)
No connection (Note 1)
No connection (Note 1)
No connection (Note 1)
No connection (Note 1)
No connection (Note 1)
No connection (Note 1)
No connection (Note 1)
No connection (Note 1)
24
25
26
27
28
29
30
31
32
CLOCK
DATA_IN
V1
V2
V3
V4
V5
V6
V7
Note 1:
May be connected to ground with no change in performance.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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March 7, 2012 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201355C
DATA SHEET • SKY12343-364LF SEVEN-BIT DIGITAL ATTENUATOR
Functional Description
The SKY12343-364LF is a seven-bit digital attenuator comprised
of a GaAs attenuator and a silicon CMOS driver. The attenuation
setting is controlled by a serial or parallel interface.
Pin 3 (P/S) selects the input mode of the attenuator. A logic low
signal applied to pin 3 enables parallel mode; a logic high enables
serial mode. Control logic levels are defined in Table 2.
Serial Data Programming
Parallel Mode Interface
from changing attenuation states as data is entered. Once the
attenuation data is loaded, the LATCH_ENABLE input should be
toggled high and then low to set the new attenuation state.
Refer to the timing diagram in Figure 4 and timing parameters in
Table 6.
Power Up and Initialization
In parallel mode, the desired attenuation state is selected using
the seven CMOS-compatible control lines, V1 through V7 (pins 26
through 32). The logic for these pins is presented in Table 3. A
logic level low on these pins places the device in the minimum
insertion loss state while a logic high places the part in the
maximum 31.75 dB insertion loss state. Intermediate levels of
attenuation are the total attenuation represented by the major bits
selected with logic high.
When the LATCH_ENABLE signal (pin 23) is held high, direct
parallel programming through pins 26 through 32 is possible,
which is useful for manual control of the device attenuation states.
For latched parallel programming, the LATCH_ENABLE signal
should be held low while the inputs to pins 26 through 32 are
applied for the desired attenuation state. When the
LATCH_ENABLE signal is pulsed high to low, the desired
attenuation state is latched.
Serial Mode Interface
Power Up.
Voltage in the allowable range from 3.3 to 5.0 V is
applied to the VDD signal (pin 2). At power up, LATCH_ENABLE
should be logic low. Immediately after power up, wait
approximately 400
μs
before setting LATCH_ENABLE logic high to
allow for internal device voltages to settle. During this period, the
device defaults to the maximum insertion loss state of 31.75 dB.
Direct Parallel Mode (P/S pin set to logic low and
LATCH_ENABLE pin set to logic high).
The SKY12343_364LF
should always be powered up with the LATCH_ENABLE signal at
logic low. Therefore, powering up in direct parallel mode is not
recommended.
The device attenuation state can be preset to any value with the
appropriate logic levels on pins 26 to 32 before power up.
Immediately after power up and the associated 400
μs
delay,
LATCH_ENABLE can be toggled to logic high. The device
attenuation state changes to the attenuation level that
corresponds to the logic levels on pins 26 to 32. If these
attenuation logic levels are allowed to float, the device powers up
in the minimum insertion loss state when LATCH_ENABLE is set to
logic high.
Latched Parallel Mode (P/S pin and LATCH_ENABLE pin set to
logic low).
The device attenuation state can be preset to any
value with the appropriate logic levels on pins 26 to 32 before
power up. Immediately after power up and the associated 400
μs
delay, the device attenuation changes to the attenuation level that
corresponds to the logic levels on pins 26 to 32 on the rising edge
of the first LATCH_ENABLE signal.
As noted above, the device attenuation state defaults to the
minimum insertion loss if pins 26 to 32 are allowed to float. In
latched parallel mode, the attenuation setting on pins 26 to 32 can
be latched into the internal register at the falling edge of the
LATCH_ENABLE signal.
Serial Addressable Mode (P/S pin set to logic high and
LATCH_ENABLE pin set to logic low).
For power up in this
mode, the parallel control input pins 26 to 32 must be set to logic
low. The device powers up in the maximum insertion loss state
and remains in that condition until the next programming word is
latched after the initial 400
μs
delay.
In serial mode, the SKY12343-364LF is programmed using an 8-
bit attenuation word and an 8-bit address word as shown in
Figure 3. The attenuation word controls the attenuation state of
the device as shown in Table 4. As with parallel mode
programming, intermediate levels of attenuation are the total
attenuation represented by the major bits selected with logic high.
For systems that use multiple SKY12343-364LF devices on a
single programming bus, up to eight devices can be individually
addressed using the address word and the device address signals
A0, A1, and A2 (pins 4, 22, and 21, respectively). A device
responds to a change in an attenuation setting when its address
matches the address defined by the address word. The address
word logic is shown in Table 5.
Note that the logic levels of bits A3 to A7 of the address word are
“don’t care” bits as shown in Figure 3.
Serial input data (DATA_IN pin) is shifted into the register on the
rising edge of the CLOCK signal (pin 24), Least Significant Bit
(LSB) first. The attenuator changes states on the rising edge of the
LATCH_ENABLE signal (pin 23) according to the most recent
seven bits of shifted data accepted since the previous falling edge
of the LATCH_ENABLE signal. The shift register must be loaded
with LATCH_ENABLE held at logic low to prevent the attenuator
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201355C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 7, 2012
3
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