Standard Products
UT8R128K32 128K x 32 SRAM
Data Sheet
March 2009
www.aeroflex.com/memories
FEATURES
15ns maximum access time
Asynchronous operation, functionally compatible with
industry-standard 128K x 32 SRAMs
CMOS compatible inputs and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volts, 1.8 volt core
Operational environment:
- Total-dose: 300 Krad(Si)
- SEL Immune: >100 MeV-cm
2
/mg
- LET
th
(0.25): 53.0 MeV-cm
2
/mg
- Memory Cell Saturated Cross Section: 1.67E-7cm
2
/bit
- Neutron Fluence: 3.0E14n/cm
2
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
Packaging options:
- 68-lead ceramic quad flatpack (6.19 grams)
Standard Microcircuit Drawing 5962-03236
- QML Q & V compliant part
INTRODUCTION
The UT8R128K32 is a high-performance CMOS static RAM
organized as 131,072 words by 32 bits. Easy memory expansion
is provided by active LOW and HIGH chip enables (E1, E2), an
active LOW output enable (G), and three-state drivers. This
device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by taking chip enable one
(E1) input LOW, chip enable two (E2) HIGH and write enable
(W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31)
is then written into the location specified on the address pins
(A0 through A16). Reading from the device is accomplished by
taking chip enable one (E1) and output enable (G) LOW while
forcing write enable (W) and chip enable two (E2) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
The 32 input/output pins (DQ0 through DQ31) are placed in a
high impedance state when the device is deselected (E1 HIGH
or E2 LOW), the outputs are disabled (G HIGH), or during a
write operation (E1 LOW, E2 HIGH and W LOW).
W
E1
E2
HHWE
LHWE
A0
A1
A2
A3
Row Select
A4
A5
A6
A7
A8
Pre-Charge Circuit
Memory Array
256K x 16
I/O Circuit
G
A9
•
•
•
Column Select
DQ(15) to DQ(0)
Low Word
Read Circuit
Data Control
DQ(31) to DQ(16)
•
•
•
Data Control
A10 A11 A12 A13A14 A15 A16
High Word
Read Circuit
Figure 1. UT8R128K32 SRAM Block Diagram
1
DEVICE OPERATION
V
SS
A0
A1
A2
A3
A4
A5
HHWE
V
SS
LHWE
W
A6
A7
A8
A9
A10
V
DD1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
SS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1
2
3
4
5
Top View
6
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
V
DD1
A11
A12
A13
A14
A15
A16
E1
G
E2
V
DD2
V
SS
NC
NC
NC
V
DD2
V
SS
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
The UT8R128K32 has six control inputs called Chip Enable 1
(E1), Chip Enable 2 (E2), Write Enable (W), Half-word Enables
(HHWE/LHWE) and Output Enable (G); 17 address inputs,
A(16:0); and 32 bidirectional data lines, DQ(15:0). E1 and E2
chip enables control device selection, active, or standby modes.
Asserting E1 and E2 enables the device, causes I
DD
to rise to its
active value, and decodes the 17 address inputs to select one of
131,072 words in the memory. W controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
Table 1. Device Operation Truth Table
G
X
W
X
E2
X
E1
H
LHWE
X
HHWE
X
I/O Mode
DQ(31:16)
3-State
DQ(15:0)
3-State
DQ(31:16)
3-State
DQ(15:0)
3-State
DQ(31:16)
3-State
DQ(15:0)
Data Out
DQ(31:16)
Data Out
DQ(15:0)
3-State
DQ(31:16)
Data Out
DQ(15:0)
Data Out
DQ(31:16)
Data In
DQ(15:0)
Data In
DQ(31:16)
3-State
DQ(15:0)
Data In
DQ(31:16)
Data In
DQ(15:0)
3-State
DQ(31:16)
DQ(15:0)
All 3-State
DQ(31:16)
DQ(15:0)
All 3-State
Mode
Standby
Figure 2. 15ns SRAM Pinout (68)
X
X
L
X
X
X
Standby
L
H
H
L
L
H
Low Half-Word
Read
PIN NAMES
A(16:0)
DQ(31:0)
E1
E2
HHWE
LWHE
Address
Data Input/Output
Chip Enable 1
(Active Low)
Chip Enable 2
(Active High)
High half-word enable
Low half-word enable
W
G
V
DD1
V
DD2
V
SS
Write Enable
Output Enable
Power (1.8V)
Power (3.3V)
X
L
H
L
L
L
L
H
H
L
L
L
L
H
H
L
H
L
High Half-Word
Read
Word Read
Word Write
Ground
X
L
H
L
L
H
Low Half-Word
Write
X
L
H
L
H
L
High Half-Word
Write
H
H
H
L
X
X
3-State
X
X
H
L
H
H
3-State
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
2
READ CYCLE
A combination of W and E2 greater than V
IH
(min) and E1 less
than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of chip enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(31:0) after the specified t
AVQV
is satisfied. Outputs
remain active throughout the entire cycle. As long as chip
enables and output enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by the latter of E1 and E2 going active
while G remains asserted, W remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
t
ETQV
is satisfied, the 32-bit word addressed by A(16:0) is
accessed and appears at the data outputs DQ(31:0).
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is t
GLQV
unless t
AVQV
or t
ETQV
have not been
satisfied.
the sixteen bidirectional pins DQ(31:0) to avoid bus
contention.
WORD ENABLES
Separate half-word enable controls (LHWE and HHWE) allow
individual 16-bit word accesses. LHWE controls the lower bits
DQ(15:0). HHWE controls the upper bits DQ(31:16). Writing
to the device is performed by asserting E1, E2 and the half-
word enables. Reading the device is performed by asserting
E1, E2, G, and the half-word enables while W is held inactive
(HIGH).
HHWE
0
0
LHWE
0
1
OPERATION
32-bit read or write cycle
16-bit high half-word read or write
cycle (low half-word bi-direction
pins DQ(15:0) are in 3 -state)
16-bit low half-word read or write
cycle (high half-word bi-direction
pins DQ(31:16) are in 3 -state)
High and low half-word bi-
directional pins remain in 3-state,
write function disabled
1
0
1
1
Operational Environment
Write Cycle
A combination of W and E1 less than V
IL
(max) and E2 greater
than V
IH
(min) defines a write cycle. The state of G is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when either G is greater than V
IH
(min), or
when W is less than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access in Figure
4a, is defined by a write terminated by W going high, with E1
and E2 still active. The write pulse width is defined by t
WLWH
when the write is initiated by W, and by t
ETWH
when the write
is initiated by E1 or E2. Unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait user must wait t
WLQZ
before applying data to the 32
bidirectional pins DQ(31:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure 4b,
is defined by a write terminated by either of E1 or E2 going
inactive. The write pulse width is defined by t
WLEF
when the
write is initiated by W, and by t
ETEF
when the write is initiated
by either E1or E2 going active. For the W initiated write, unless
the outputs have been previously placed in the high-impedance
state by G, the user must wait t
WLQZ
before applying data to
The UT8R128K32 SRAM incorporates special design, layout,
and process features which allows operation in a limited
environment.
Table 2. Operational Environment Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
300K
8.9x10
-10
rad(Si)
Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup to particles >100MeV-cm
2
/mg.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Supply Sequencing
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD1
V
DD2
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
Thermal resistance, junction-to-case
2
DC input current
LIMITS
-0.3 to 2.1V
-0.3 to 3.8V
-0.3 to 3.8V
-65 to +150°C
1.2W
+150°C
5°C/W
±
5 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD1
V
DD2
T
C
PARAMETER
Positive supply voltage
Positive supply voltage
Case temperature range
LIMITS
1.7 to 1.9V
1
3.0 to 3.6V
(P) Screening: 25°C
(C) Screening: -55 to +125°C
(W) Screening: -40 to +125°C
0V to V
DD2
V
IN
DC input voltage
Notes:
1. For increased noise immunity, supply voltage (V
DD1
) can be increased to 2.0V. If not tested, all applicable DC and AC characteristics are guranteed by characterization
at VDD1 (max) = 2.0V.
4
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
Unless otherwise noted, Tc is per the temperature ordered
SYMBOL
V
IH
V
IL
V
OL
V
OH
C
IN1
C
IO1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O
capacitance
Input leakage current
Three-state output leakage
current
I
OL
= 8mA,V
DD2
=V
DD2
(min)
I
OH
= -4mA,V
DD2
=V
DD2
(min)
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
IN
= V
DD2
and V
SS
V
O
= V
DD2
and V
SS
V
DD2
= V
DD2
(max),
G = V
DD2
(max)
V
DD2
= V
DD2
(max), V
O
= V
DD2
V
DD2
= V
DD2
(max), V
O
= V
SS
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
-0.2V , I
OUT
= 0
V
DD2
= V
DD2
(max)
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
-0.2V, I
OUT
= 0
V
DD2
= V
DD2
(max)
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
-0.2V , I
OUT
= 0
V
DD1
= V
DD1
(max),
V
DD2
= V
DD2
(max)
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
-0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max),
V
DD2
= V
DD2
(max)
V
DD1
= 1.9V
V
DD1
= 2.0V
V
DD1
= 1.9V
V
DD1
= 2.0V
-2
-2
.8*V
DD2
12
12
2
2
CONDITION
MIN
.7*V
DD2
.3*V
DD2
.2*V
DD2
MAX
UNIT
V
V
V
V
pF
pF
μA
μA
I
OS2, 3
I
DD1
(OP
1
)
Short-circuit output current
-100
+100
mA
V
DD1
Supply current
operating @ 1MHz
V
DD1
Supply current
operating @ 66MHz
V
DD2
Supply current
operating @ 1MHz
15
18
85
105
1
mA
mA
mA
mA
mA
I
DD1
(OP
2
)
I
DD2
(OP
1
)
I
DD2
(OP
2
)
V
DD2
Supply current
operating @ 66MHZ
12
mA
5
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