DUAL MONOSTABLE
MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
Each multivibrator of the LS221 features a negative-transition-triggered
input and a positive-transition-triggered input either of which can be used as
an inhibit input.
Pulse triggering occurs at a voltage level and is not related to the transition
time of the input pulse. Schmitt-trigger input circuitry for B input allows
jitter-free triggering for inputs as slow as 1 volt / second, providing the circuit
with excellent noise immunity. A high immunity to VCC noise is also provided
by internal latching circuitry.
Once triggered, the outputs are independent of further transitions of the
inputs and are a function of the timing components. The output pulses can be
terminated by the overriding clear. Input pulse width may be of any duration
relative to the output pulse width. Output pulse width may be varied from 35
nanoseconds to a maximum of 70 s by choosing appropriate timing
components. With Rext = 2.0 kΩ and Cext = 0, a typical output pulse of 30
nanoseconds is achieved. Output rise and fall times are independent of pulse
length.
Pulse width stability is achieved through internal compensation and is
virtually independent of VCC and temperature. In most applications, pulse
stability will only be limited by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges
for greater than six decades of timing capacitance (10 pF to 10
µF),
and
greater than one decade of timing resistance (2.0 to 70 kΩ for the
SN54LS221, and 2.0 to 100 kΩ for the SN74LS221). Pulse width is defined
by the relationship: tw(out) = CextRext ln 2.0
≈
0.7 Cext Rext; where tW is in ns
if Cext is in pF and Rext is in kΩ . If pulse cutoff is not critical, capacitance up
to 1000
µF
and resistance as low as 1.4 kΩ may be used. The range of
jitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature.
•
SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot
•
Overriding Clear Terminates Output Pulse
•
Pin Out is Identical to SN54 / 74LS123
SN54/74LS221
DUAL MONOSTABLE
MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
(TOP VIEW)
VCC
16
1 Rext/ 1
Cext Cext
15
14
Q
Q
CLR
1Q
13
2Q
12
2
CLR
11
2B
10
2A
9
VCC
CLR
Q
Q
4
1Q
5
2Q
6
2
Cext
8
7
2 Rext/ GND
Cext
Cext
Rext
+
R/C
L
X
X
H
H
*
°
FUNCTION TABLE
(EACH MONOSTABLE)
INPUTS
CLEAR
A
X
H
X
L
±
L
B
X
X
L
°
H
H
MAXIMUM
OUTPUT PULSE
LENGTH
49 s
70 s
OUTPUTS
Q
L
L
L
Q
H
H
H
1
1A
2
1B
3
1
CLR
*See operational notes — Pulse Trigger Modes
TYPE
SN54LS221
SN74LS221
positive logic: Low input to clear resets Q low and
positive logic:
Q high regardless of dc levels at A
positive logic:
or B inputs.
TYPICAL
POWER
DISSIPATION
23 mW
23 mW
FAST AND LS TTL DATA
5-1
SN54/74LS221
OPERATIONAL NOTES
Once in the pulse trigger mode, the output pulse width is
determined by tW = RextCextIn2, as long as Rext and Cext are
within their minimum and maximum valves and the duty cycle
is less than 50%. This pulse width is essentially independent
of VCC and temperature variations. Output pulse widths varies
typically no more than
±0.5%
from device to device.
If the duty cycle, defined as being 100
•
tW where T is the
T
input
period of the input pulse, rises above 50%, the output pulse
width will become shorter. If the duty cycle varies between
low and high valves, this causes the output pulse width to
vary in length, or jitter. To reduce jitter to a minimum, Rext
should be as large as possible. (Jitter is independent of Cext).
With Rext = 100K, jitter is not appreciable until the duty cycle
approaches 90%.
Although the LS221 is pin-for-pin compatible with the
LS123, it should be remembered that they are not functionally
identical. The LS123 is retriggerable so that the output is
dependent upon the input transitions once it is high. This is not
the case for the LS221. Also note that it is recommended to
externally ground the LS123 Cext pin. However, this cannot be
done on the LS221.
The SN54LS/74LS221 is a dual, monolithic, non-retrigger-
able, high-stability one shot. The output pulse width, tW can be
varied over 9 decades of timing by proper selection of the
external timing components, Rext and Cext.
Pulse triggering occurs at a voltage level and is, therefore,
independent of the input slew rate. Although all three inputs
have this Schmitt-trigger effect, only the B input should be
used for very long transition triggers (≥1.0
µV/s).
High
immunity to VCC noise (typically 1.5 V) is achieved by internal
latching circuitry. However, standard VCC bypassing is
strongly recommended.
The LS221 has four basic modes of operation.
Clear Mode:
If the clear input is held low, irregardless of
the previous output state and other input
states, the Q output is low.
Inhibit Mode: If either the A input is high or the B input is
low, once the Q output goes low, it cannot be
retriggered by other inputs.
Pulse Trigger
Mode:
A transition of the A or B inputs as indicated
in the functional truth table will trigger the Q
output to go high for a duration determined
by the tW equation described above; Q will
go low for a corresponding length of time.
The Clear input may also be used to trigger
an output pulse, but special logic precondi-
tioning on the A or B inputs must be done as
follows:
Following any output triggering action
using the A or B inputs, the A input must
be set high OR the B input must be set
low to allow Clear to be used as a trigger.
Inputs should then be set up per the truth
table (without triggering the output) to
allow Clear to be used a trigger for the
output pulse.
If the Clear pin is routinely being used to
trigger the output pulse, the A or B inputs
must be toggled as described above
before and between each Clear trigger
event.
Once triggered, as long as the output
remains high, all input transitions (except
overriding Clear) are ignored.
Overriding
Clear Mode:
If the Q output is high, it may be forced low
by bringing the clear input low.
FAST AND LS TTL DATA
5-2
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