REJ09B0024-0600
8
H8/3802, H8/38004,
H8/38002S, H8/38104
Group
Hardware Manual
Renesas 8-Bit Single-Chip Microcomputer
H8 Family / H8/300L Super Low Power Series
H8/3802 Group
H8/3802
H8/3801
H8/3800
H8/38004
H8/38003
H8/38002
H8/38001
H8/38000
H8/38002S Group
H8/38002S
H8/38001S
H8/38000S
H8/38104
H8/38103
H8/38102
H8/38101
H8/38100
H8/38004 Group
H8/38104 Group
Rev. 6.00
Revision Date: Mar 15, 2005
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 6.00 Mar 15, 2005 page ii of l
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 6.00 Mar 15, 2005 page iii of l
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 6.00 Mar 15, 2005 page iv of l
Preface
The H8/3802 Group, H8/38004 Group, and H8/38104 Group are single-chip microcomputers
made up of the high-speed H8/300L CPU employing Renesas technology’s original architecture as
their cores, and the peripheral functions required to configure a system. The H8/300L CPU has an
instruction set that is compatible with the H8/300 CPU. Below is a table listing the product
specifications for each group.
H8/3802 Group
Item
ZTAT
Memory
ROM
RAM
Operating 4.5 to 5.5 V
voltage
2.7 to 5.5 V
and
operating 1.8 to 5.5 V
frequency
2.7 to 3.6 V
1.8 to 3.6 V
I/O ports
Input
Output
I/O
Timers
Clock (timer A)
Compare (timer F)
AEC
WDT
WDT (discrete)
SCI
UART/Clock
frequency
1 ch
1 ch
1 ch
16 k
1k
16 MHz
10 MHz
4 MHz
—
—
9
6
39
1
1
1
H8/38004 Group
H8/38002S
Group
H8/38104 Group
Mask ROM Flash ROM Mask ROM Mask ROM Flash ROM Mask ROM
8 k to 16 k
512 or 1 k
16 MHz
10 MHz
4 MHz
—
—
9
6
39
1
1
1
16 k/32 k
1k
—
—
—
10 MHz
4 MHz (2.2 V
or more)
9
6
39
1
1
1
1
1
1 ch
1 ch
32 k
1k
16 MHz
16 MHz
—
—
—
9
5
39
1
1
1
8 k to 16 k
512 k
—
—
—
10 MHz
4 MHz
9
6
39
1
1
1
1
1
1 ch
1
1 ch
16 k/32 k
1k
20 MHz
20 MHz
—
—
—
9
5
39
1
1
1
8 k to 32 k
512 or 1 k
20 MHz
20 MHz
—
—
—
9
5
39
1
1
1
A-D (resolution
×
input
channels)
LCD
seg
com
External interrupt
(internal wakeup)
POR (power-on reset)
LVD
Package
10 bit
×
4 ch 10 bit
×
4 ch 10 bit
×
4 ch 10 bit
×
4 ch 10 bit
×
4 ch 10 bit
×
4 ch 10 bit
×
4 ch
25
4
11(8)
—
—
FP-64A
FP-64E
DP-64S
25
4
11(8)
—
—
FP-64A
FP-64E
DP-64S
die
die
25
4
11(8)
—
—
FP-64A
FP-64E
25
4
11(8)
—
—
FP-64A
FP-64E
25
4
11(8)
—
—
FP-64A
FP-64K*
25
4
11(8)
1
1
FP-64A
FP-64E
25
4
11(8)
1
1
FP-64A
FP-64E
Operating temperature
Standard specifications: –20 to 75°C, WTR: –40 to 85°C
Note:
*
Under development.
Rev. 6.00 Mar 15, 2005 page v of l
FPGA/CPLD
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