PRELIMINARY DATA SHEET
256MB Unbuffered SDRAM Micro DIMM
HB52RF328GB-B (32M words
×
64 bits, 1 bank)
HB52RD328GB-B (32M words
×
64 bits, 1 bank)
Description
The HB52RF328GB and HB52RD328GB are a 32M
×
64
×
1 banks Synchronous Dynamic RAM Micro Dual
In-line Memory Module (Micro DIMM), mounted 8
pieces of 256M bits SDRAM (HM522805BTB/BLTB)
sealed in TCP package and 1 piece of serial EEPROM
(2k bits EEPROM) for Presence Detect (PD). An
outline of the products is 144-pin Zig Zag Dual tabs
socket type compact and thin package. Therefore,
they make high density mounting possible without
surface mount technology. They provide common data
inputs and outputs.
Decoupling capacitors are
mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
•
144-pin Zig Zag Dual tabs socket type (dual lead out)
Outline: 38.00mm (Length)
×
30.00mm (Height)
×
3.80mm (Thickness)
Lead pitch: 0.50mm
•
3.3V power supply
•
Clock frequency: 133MHz/100MHz (max.)
•
LVTTL interface
•
Data bus width:
×
64 Non parity
•
Single pulsed /RAS
•
4 Banks can operates simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8
•
2 variations of burst sequence
Sequential
Interleave
•
Programmable /CE latency (CL): 2, 3
•
Byte control by DQMB
•
Refresh cycles: 8192 refresh cycles/64ms
•
2 variations of refresh
Auto refresh
Self refresh
•
Low self refresh current : HB52RF328GB-xxBL
: HB52RD328GB-xxBL
EO
Document No. E0202H10 (Ver. 1.0)
Date Published August 2001 (K)
Printed in Japan
URL: http://www.elpida.com
L
o
Pr
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
du
ct
C
Elpida Memory, Inc. 2001
HB52RF328GB-B, HB52RD328GB-B
Ordering Information
Part number
HB52RF328GB-75B*
HB52RF328GB-75BL*
1
HB52RD328GB-A6B
HB52RD328GB-A6BL
HB52RD328GB-B6B*
2
HB52RD328GB-B6BL*
2
1
Clock frequency
MHz (max.)
133
133
100
100
100
100
/CE latency
3
3
2, 3
2, 3
3
3
Package
Micro DIMM (144-pin)
Contact pad
Gold
Notes: 1. 100MHz operation at /CE latency = 2.
2. 66MHz operation at /CE latency = 2.
EO
Front side
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
VCC
A0
A1
A2
VSS
Pin Configurations
Front Side
1pin
2pin
143pin
144pin
Preliminary Data Sheet E0202H10 (Ver. 1.0)
L
Pin name
Pin No.
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
DQMB0
DQMB1
Back Side
o
Pr
Back side
Pin No.
Pin name
NC
2
VSS
VSS
4
DQ32
NC
NC
6
8
DQ33
DQ34
VCC
10
DQ35
DQ16
12
VCC
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
14
16
18
20
22
24
26
28
30
32
34
36
DQ36
DQ37
DQ38
DQ39
VSS
VCC
A3
A4
A5
VSS
Pin name
Pin No.
74
76
78
80
82
84
86
88
90
Pin name
CK1
VSS
NC
NC
VCC
DQ48
DQ49
DQ50
DQ51
VSS
du
92
94
DQMB4
DQMB5
96
98
100
102
104
106
A7
108
DQ52
DQ53
DQ54
DQ55
ct
VCC
BA0
VSS
2
HB52RF328GB-B, HB52RD328GB-B
Front side
Pin No.
37
39
41
43
45
47
49
51
53
Pin name
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
Pin No.
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
Pin name
A9
A10 (AP)
VCC
DQMB2
DQMB3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC
Back side
Pin No.
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Pin name
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
NC
NC
CKE0
VCC
/CE
NC
A12
NC
Pin No.
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin name
BA1
A11
VCC
DQMB6
DQMB7
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
EO
55
57
NC
59
NC
61
63
CK0
VCC
/RE
/W
65
67
69
71
/S0
NC
Pin Description
Pin name
A0 to A12
L
139
141
143
o
Pr
Function
Address input
— Row address
A0 to A12
— Column address A0 to A9
Bank select address
Data-input/output
Chip select
Row address asserted bank enable
Column address asserted
Write enable
BA0, BA1
DQ0 to DQ63
/S0
/RE
/CE
/W
DQMB0 to DQMB7
CK0, CK1
CKE0
SDA
SCL
VCC
VSS
NC
Byte input/output mask
Clock input
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Power supply
Ground
No connection
du
ct
Preliminary Data Sheet E0202H10 (Ver. 1.0)
3
HB52RF328GB-B, HB52RD328GB-B
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
7
8
9
1
Function described
Number of bytes used by module
manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column addresses bits
Number of banks
Module data width
Module data width (continued)
Module interface signal levels
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
80
08
04
0D
0A
01
40
00
01
75
A0
54
60
00
82
08
00
01
0F
04
06
01
01
Comments
128
256byte
SDRAM
13
10
1
64
0 (+)
LVTTL
CL = 3
EO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(-B6) 15ns
24
(-B6) 8ns
25
SDRAM cycle time
(highest /CE latency)
(-75) 7.5ns
(-A6, -B6) 10ns
SDRAM access from Clock (highest
/CE latency)
0
(-75) 5.4ns
Module configuration type
Refresh rate/type
SDRAM width
Error checking SDRAM width
SDRAM device attributes:
minimum clock delay for back-to-
back random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes: number of
banks on SDRAM device
SDRAM device attributes:
/CE latency
SDRAM device attributes:
/S latency
SDRAM device attributes:
/W latency
SDRAM module attributes
SDRAM device attributes: General
SDRAM cycle time
(2nd highest /CE latency)
(-75/A6) 10ns
SDRAM access from Clock (2nd
highest /CE latency)
(-75/A6) 6ns
SDRAM cycle time
(3rd highest /CE latency)
Undefined
Preliminary Data Sheet E0202H10 (Ver. 1.0)
L
(-A6, -B6) 6ns
0
0
1
0
0
Non parity
Normal
(7.8125µs)
Self refresh
×
8
—
1 CLK
1, 2, 4, 8
4
2, 3
0
0
o
Pr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
du
0
00
0
0E
0
A0
CL = 2
0
F0
0
60
0
0
80
00
Unbuffer
V
CC
± 10%
ct
4
HB52RF328GB-B, HB52RD328GB-B
Byte No.
26
27
28
Function described
SDRAM access from Clock (3rd
highest /CE latency)
Undefined
Minimum row precharge time
Row active to row active min
(-75)
(-A6, -B6)
29
30
/RE to /CE delay min
Minimum /RE pulse width
(-75)
(-A6, -B6)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
1
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
×
0
0
00
14
0F
14
14
2D
32
40
15
20
08
10
15
20
08
10
00
12
52
B9
29
07
00
××
48
42
*
2
(ASCII-8bit code)
H
B
5
2
20ns
15ns
20ns
20ns
45ns
50ns
256M byte
1.5ns
2.0ns
0.8ns
1.0ns
1.5ns
2.0ns
0.8ns
1.0ns
Future use
Rev. 1.2B
82
185
41
HITACHI
Comments
EO
31
32
(-A6, -B6)
33
(-A6, -B6)
34
(-A6, -B6)
35
(-A6, -B6)
36 to 61
62
63
(-A6B/BL)
(-B6B/BL)
64
65 to 71
72
73
74
75
76
77
78
(-A6, -B6)
79
80
81
82
83
84
Density of each bank on module
Address and command signal input
setup time
(-75)
Address and command signal input
hold time
(-75)
Data signal input setup time
(-75)
Data signal input hold time
(-75)
Superset information
SPD data revision code
Checksum for bytes 0 to 62
(-75B/BL)
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
(-75)
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Preliminary Data Sheet E0202H10 (Ver. 1.0)
L
o
Pr
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
0
×
0
×
0
×
0
×
0
×
0
×
0
×
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
1
1
0
1
1
0
du
1
0
35
32
0
52
R
F
0
46
0
44
D
3
2
8
1
0
0
1
0
1
33
32
38
47
42
2D
ct
G
B
5
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