DATA SHEET
256MB Unbuffered DDR SDRAM DIMM
HB54A2568FM-A75B/B75B/10B
(32M words
×
64 bits, 1 Bank)
HB54A2569FM-A75B/B75B/10B
(32M words
×
72 bits, 1 Bank)
Description
The HB54A2568FM, HB54A2569FM are Double Data
Rate (DDR) SDRAM Module, mounted 256M bits DDR
SDRAM (HM5425801BTT) sealed in TSOP package,
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD).
The HB54A2568FM is
organized as 32M
×
64
×
1 bank mounted 8 pieces of
256M bits DDR SDRAM. The HB54A2569FM is
organized as 32M
×
72
×
1 bank mounted 9 pieces of
256M bits DDR SDRAM. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. An outline of the products is
184-pin socket type package (dual lead out).
Therefore, it makes high density mounting possible
without surface mount technology. It provides common
data inputs and outputs. Decoupling capacitors are
mounted beside each TSOP on the module board.
Features
•
184-pin socket type package (dual lead out)
Outline: 133.35mm (Length)
×
31.75mm (Height)
×
4.00mm (Thickness)
Lead pitch: 1.27mm
•
2.5V power supply (VCC/VCCQ)
•
SSTL-2 interface for all inputs and outputs
•
Clock frequency: 143MHz/133MHz/125MHz (max.)
•
Data inputs, outputs and DM are synchronized with
DQS
•
4 banks can operate simultaneously and
independently (Component)
•
Burst read/write operation
•
Programmable burst length: 2, 4, 8
Burst read stop capability
•
Programmable burst sequence
Sequential
Interleave
•
Start addressing capability
Even and Odd
•
Programmable /CAS latency (CL): 2, 2.5
•
8192 refresh cycles: 7.8µs (8192/64ms)
•
2 variations of refresh
Auto refresh
Self refresh
EO
Document No. E0088H40 (Ver. 4.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2001-2002
Hitachi,
Ltd. 2000
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
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Pr
uc
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HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
/CAS
/WE
/S0
Function
Address input
Row address
Column address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for DQ circuit
Power for serial EEPROM
Input reference voltage
A0 to A12
A0 to A9
Bank select address
EO
CKE0
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS8
SCL
SDA
SA0 to SA2
VCC
VCCQ
VCCSPD
VREF
VSS
VCCID
NC
DM0 to DM8/DQS9 to DQS17
Data Sheet E0088H40 (Ver. 4.0)
L
od
Pr
Ground
VCC identification flag
No connection
uc
t
4
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
1
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM banks
Module data width
HB54A2568FM
HB54A2569FM
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
Bit5 Bit4
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
Bit3
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
Bit2
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
Bit1 Bit0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
Hex value
80
08
07
0D
0A
01
40
48
00
04
70
75
80
75
80
00
02
82
08
00
Comments
128
256 byte
SDRAM DDR
13
10
1
64 bits
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*
5
EO
7
8
9
-B75B
-10B
10
-10B
11
12
13
14
15
16
17
18
19
20
21
22
23
-B75B/10B
24
-10B
Voltage interface level of this assembly 0
0
0
1
0
1
0
0
1
0
DDR SDRAM cycle time, CL = X
-A75B
SDRAM access from clock (tAC)
-A75B/B75B
DIMM configuration type
HB54A2568FM
HB54A2569FM
0.75ns*
5
0.8ns*
5
None
ECC
7.8 µs
Self refresh
×
8
None
×
8
1 CLK
2, 4, 8
4
2, 2.5
0
1
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
HB54A2568FM
HB54A2569FM
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
CLX - 0.5
-A75B
Maximum data access time (tAC) from
clock at CLX - 0.5
0
-A75B/B75B
1
Data Sheet E0088H40 (Ver. 4.0)
L
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Pr
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
1
0
08
01
0E
04
0C
01
02
uc
20
Unbuffered
± 0.2V
C0
75
CL = 2*
5
A0
t
0.75ns*
5
0.8ns*
5
75
80
5
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