DATA SHEET
512MB Registered DDR SDRAM DIMM
HB54A5129F1-B75B/10B
(64M words
×
72 bits, 1 Rank)
Description
The HB54A5129F1 is a 64M
×
72
×
1 rank Double Data
Rate (DDR) SDRAM Module, mounted 18 pieces of
256Mbits DDR SDRAM sealed in TSOP package, 1
piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD). Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2-bit
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. An outline of the products is
184-pin socket type package (dual lead out).
Therefore, it makes high density mounting possible
without surface mount technology. It provides common
data inputs and outputs. Decoupling capacitors are
mounted beside each TSOP on the module board.
Features
•
184-pin socket type package (dual lead out)
Outline: 133.35mm (Length)
×
43.18 (Height)
×
4.00mm (Thickness)
Lead pitch: 1.27mm
•
2.5V power supply (VCC/VCCQ)
•
SSTL-2 interface for all inputs and outputs
•
Clock frequency: 133MHz/125MHz (max.)
•
Data inputs and outputs are synchronized with DQS
•
4 banks can operate simultaneously and
independently (Component)
•
Burst read/write operation
•
Programmable burst length: 2, 4, 8
Burst read stop capability
•
Programmable burst sequence
Sequential
Interleave
•
Start addressing capability
Even and Odd
•
Programmable /CAS latency (CL): 3, 3.5
•
8192 refresh cycles: 7.8µs (8192/64ms)
•
2 variations of refresh
Auto refresh
Self refresh
EO
Document No. E0090H60 (Ver. 6.0)
Date Published April 2003 (K) Japan
URL: http://www.elpida.com
Elpida
Memory,Inc. 2001-2003
Hitachi,
Ltd. 2000
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
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HB54A5129F1-B75B/10B
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
/CAS
/WE
/S0
Function
Address input
Row address
Column address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input and output data strobe
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for DQ circuit
Power for serial EEPROM
Input reference voltage
A0 to A12
A0 to A9, A11
Bank select address
EO
CKE0
CK0
/CK0
DQS0 to DQS8
SCL
SDA
SA0 to SA2
VCC
VCCQ
VCCSPD
VREF
VSS
VCCID
/RESET
NC
DM0 to DM8/DQS9 to DQS17
Data Sheet E0090H60 (Ver. 6.0)
L
od
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Ground
VCC identification flag
Reset pin (forces register inputs low)
No connection
uc
t
4
HB54A5129F1-B75B/10B
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
7
8
9
1
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
Bit3
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
Bit2
0
0
1
1
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
Bit1 Bit0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
Hex value
80
08
07
0D
0B
01
48
00
04
75
80
75
80
02
82
04
04
01
0E
04
Comments
128
256 byte
SDRAM DDR
13
11
1
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*
5
EO
-10B
10
-10B
11
12
13
14
15
16
17
18
19
20
21
22
23
24
-10B
25
26
27
28
29
Voltage interface level of this assembly 0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
DDR SDRAM cycle time, CL = X
-B75B
SDRAM access from clock (tAC)
-B75B
0.75ns*
5
0.8ns*
5
ECC
7.8 µs
Self refresh
×
4
×
4
1 CLK
2, 4, 8
4
2/2.5
0
1
Registered
± 0.2V
CL = 2*
5
0.75ns*
5
0.8ns*
5
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
1
CLX - 0.5
Maximum data access time (tAC) from
clock at CLX - 0.5
0
-B75B
Minimum clock cycle time at
0
CLX - 1
Maximum data access time (tAC) from
0
clock at CLX - 1
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
Data Sheet E0090H60 (Ver. 6.0)
L
od
Pr
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0C
01
02
26
C0
A0
75
uc
80
00
00
50
20ns
t
15ns
20ns
3C
50
5
单片机
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