TM
HD-15531
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15531 is a high performance CMOS device
intended to service the requirements of MIL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two sec-
tions, an Encoder and a Decoder. These sections operate
independently of each other, except for the master reset and
word length functions. This circuit provides many of the
requirements of MIL-STD-1553. The Encoder produces the
sync pulse and the parity bit as well as the encoding of the
data bits. The Decoder recognizes the sync pulse and identi-
fies it as well as decoding the data bits and checking parity.
The HD-15531 also surpasses the requirements of MIL-
STD-1553 by allowing the word length to be programmable
(from 2 to 28 data bits). A frame consists of three bits for
sync followed by the data word (2 to 28 data bits) followed by
one bit of parity, thus, the frame length will vary from 6 to 32
bit periods. This chip also allows selection of either even or
odd parity for the Encoder and Decoder separately.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MIL-STD-1553 over both temperature and
voltage. For high speed applications the 15531B will support
a 2.5 Megabit/sec data rate.
The HD-15531 can also be used in many party line digital
data communications applications, such as a local area net-
work or an environmental control system driven from a single
twisted pair of fiber optic cable throughout a building.
March 1997
Features
• Support of MIL-STD-1553
• Data Rate (15531B) . . . . . . . . . . . . . . . .2.5 Megabit/Sec
• Data Rate (15531) . . . . . . . . . . . . . . . . .1.25 Megabit/Sec
• Variable Frame Length to 32 Bits
• Sync Identification and Lock-In
• Separate Manchester II Encode, Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
PDIP
CERDIP
TEMP. RANGE
(
o
C)
-40 to 85
-40 to 85
-55 to 125
1.25MBIT
/SEC
-
HD1-15531-9
HD1-15531-8
5962-
9054901MQA
5962-
9054902MQA
2.5MBIT
/SEC
PKG.
NO.
HD3-15531B-9
E40.6
HD1-15531B-9
F40.6
HD1-15531B-8
F40.6
HD1-15531
DESC
(CERDIP)
-55 to 125
F40.6
-55 to 125
HD1-15531B
F40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2961.1
1
HD-15531
Pinout
HD-15531 (CERDIP, PDIP)
TOP VIEW
V
CC
VALID WORD
TAKE DATA’
TAKE DATA
SERIAL DATA OUT
SYNCHR DATA
SYNCHR DATA SEL
SYNCHR CLK
DECODER CLK
1
2
3
4
5
6
7
8
9
40 COUNT C
1
39 COUNT C
4
38 DATA SYNC
37 ENCODER CLK
36 COUNT C
3
35 NC
34 ENCODER SHIFT CLK
33 SEND CLK IN
32 SEND DATA
31 ENCODER PARITY SEL
30 SYNC SEL
29 ENCODER ENABLE
28 SERIAL DATA IN
27 BIPOLAR ONE OUT
26 OUTPUT INHIBIT
25
24
BIPOLAR ZERO OUT
SYNCHR CLK SEL 10
BIPOLAR ZERO IN 11
BIPOLAR ONE IN 12
UNIPOLAR DATA IN 13
DECODER SHIFT CLK 14
TRANSITION SEL 15
NC 16
COMMAND SYNC 17
DECODER PARITY SEL 18
DECODER RESET 19
COUNT C
0
20
÷
6 OUT
23 COUNT C2
22 MASTER RESET
21 GND
Block Diagrams
ENDODER
21
22
33
24
GND
MASTER RESET
SEND CLK IN
V
CC
OUTPUT
INHIBIT
1
÷
6 OUT
÷
2
÷
6
CHARACTER
FORMER
27
26
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
25
37
ENCODER
CLK
BIT
COUNTER
32
20
C
0
40
C
1
23
C
2
36
C
3
39
C
4
34
28
29
30
31
SEND
DATA
SERIAL
DATA IN
SYNC
SELECT
ENCODER
PARITY
SELECT
ENCODER
SHIFT
CLK
ENCODER
ENABLE
2
HD-15531
DECODER
7
8
SYNCHRONOUS
DATA SELECT
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
BIPOLAR
ONE IN
13
12
11
TRANSITION
FINDER
SYNCHRONOUS
DATA
4
TAKE DATA
COMMAND SYNC
DATA SYNC
5
SERIAL
DATA OUT
VALID WORD
PARITY
SELECT
DECODER
SHIFT CLK
DATA
SELECT
GATE
CHARACTER
IDENTIFIER
17
DECODER
CLK
DECODER
CLK SELECT
SYNCHRONOUS
CLK
SYNCHRONOUS
CLK SELECT
MASTER
RESET
9
15 SYNCHRONIZER
8
CLOCK
SELECT
DATA
BIT
RATE
CLK
2
PARITY
CHECK 16
14
10
22
DECODER
RESET
19
BIT
COUNTER
23
C
1
C
2
36
C
3
39
C
4
3
TAKE DATA’
20 40
C
0
Pin Description
PIN
NUMBER
1
2
3
O
O
TYPE
V
CC
VALID WORD
TAKE DATA’
NAME
SECTION
Both
Decoder
Decoder
DESCRIPTION
Positive supply pin. A 0.1µF decoupling capacitor from V
CC
(pin 1) to GROUND
(pin 21) is recommended.
Output high indicates receipt of a valid word, (valid parity and no Manchester
errors).
A continuous, free running signal provided for host timing or data handling. When
data is present on the bus, this signal will be synchronized to the incoming data
and will be identical to TAKE DATA.
Output is high during receipt of data after identification of a valid sync pulse and
two valid Manchester bits.
Delivers received data in correct NRZ format.
Input presents Manchester data directly to character identification logic.
SYNCHRONOUS DATA SELECT must be held high to use this input. If not
used, this pin must be held high.
In high state allows the synchronous data to enter the character identification
logic. Tie this input low for asynchronous data.
Input provides externally synchronized clock to the decoder, for use when re-
ceiving synchronous data. This input must be tied high when not in use.
Input drives the transition finder, and the synchronizer which in turn supplies the
clock to the balance of the decoder. Input a frequency equal to 12X the data rate.
In high state directs the SYNCHRONOUS CLOCK to control the decoder char-
acter identification logic. A low state selects the DECODER CLOCK.
A high input should be applied when the bus is in its negative state. This pin must
be held high when the unipolar input is used.
A high input should be applied when the bus is in its positive state. This pin must
he held low when the unipolar input is used.
With pin 11 high and pin 12 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
4
5
6
O
O
I
TAKE DATA
SERIAL DATA OUT
SYNCHRONOUS
DATA
SYNCHRONOUS
DATA SELECT
SYNCHRONOUS
CLOCK
DECODER CLOCK
SYNCHRONOUS
CLOCK SELCT
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
Decoder
Decoder
Decoder
7
8
9
10
11
12
13
I
I
I
I
I
I
I
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
3
HD-15531
Pin Description
PIN
NUMBER
14
15
TYPE
O
I
(Continued)
NAME
DECODER SHIFT
CLOCK
TRANSITION SE-
LECT
NC
SECTION
Decoder
Decoder
DESCRIPTION
Output which delivers a frequency (DECODER CLOCK + 1 2), synchronous by
the recovered serial data stream.
A high input to this pin causes the transition finder to synchronize on every tran-
sition of input data. A low input causes the transition finder to synchronize only
on mid-bit transitions.
Not connected.
Output of a high from this pin occurs during output of decoded data which was
preceded by a Command (or Status) synchronizing character.
An input for parity sense, calling for even parity with input high and odd parity
with input low.
A high input to this pin during a rising edge of DECODER SHIFT CLOCK resets
the decoder bit counting logic to a condition ready for a new word.
One of five binary inputs which establish the total bit count to be encoded or de-
coded.
Supply pin.
A high on this pin clears 2:1 counters in both encoder and decoder, and resets
the
÷
6 circuit.
See pin 20.
Output from 6:1 divider which is driven by the ENCODER CLOCK.
An active low output designed to drive the zero or negative sense of a bipolar
line driver.
A low on this pin forces pin 25 and 27 high, the inactive states.
An active low output designed to drive the one or positive sense of a bipolar line
driver.
Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK.
A high on this pin initiates the encode cycle. (Subject to the preceding cycle be-
ing complete).
Actuates a Command sync for an input high and Data sync for an input low.
Sets transmit parity odd for a high input, even for a low input.
Is an active high output which enables the external source of serial data.
Clock input at a frequency equal to the data rate X2, usually driven by
÷
6 output.
Output for shifting data into the Encoder. The Encoder samples SDI pin-28 on
the low-to-high transition of ESC.
Not connected.
See pin 20.
Input to the 6:1 divider, a frequency equal to 12 times the data rate is usually
input here.
Output of a high from this pin occurs during output of decoded data which was
preceded by a data synchronizing character.
See pin 20.
See pill 20.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I
I
O
I
I
I
I
O
O
I
O
I
I
I
I
O
I
O
O
I
I
I
Blank
Decoder
Decoder
Decoder
Both
Both
Both
Both
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Blank
Both
Encoder
Decoder
Both
Both
COMMAND SYNC
DECODER PARITY
SELECT
DECODER RESET
COUNT C0
GROUND
MASTER RESET
COUNT C2
÷
6 OUT
BIPOLAR ZERO
OUT
OUTPUT INHIBIT
BIPOLAR ONE OUT
SERIAL DATA IN
ENCODER ENABLE
SYNC SELECT
ENCODER PARITY
SELECT
SEND DATA
SEND CLOCK IN
ENCODER SHIFT
CLOCK
NC
COUNT C3
ENCODER CLOCK
DATA SYNC
COUNT C4
COUNT C1
4
HD-15531
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK. The frame length is set by pro-
gramming the COUNT inputs. Parity is selected by
programming ENCODER PARITY SELECT high for odd par-
ity or low for even parity.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK
1
.
This cycle lasts for one word length or K + 4 ENCODER
SHIFT CLOCK periods, where K is the number of bits to be
sent. At the next low-to-high transition of the ENCODER
SHIFT CLOCK, a high SYNC SELECT input actuates a
Command sync or a low will produce a Data sync for the
word
2
. When the Encoder is ready to accept data, the
SEND DATA output will go high for K ENCODER SHIFT
CLOCK periods
4
. During these K periods the data should
TIMING
SEND CLOCK
ENCODER
SHIFT CLOCK
ENCODER
ENABLE
SYNC
SELECT
SEND
DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4 BIT K-5 BIT 4 BIT 3
BIT 2
BIT 1
be clocked into the SERIAL DATA input with every high-to-
low transition of the ENCODER SHIFT CLOCK
3
-
4
so it
can be sampled on the low-to-high transition. After the sync
and Manchester II encoded data are transmitted through the
BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder
adds on an additional bit with the parity for that word
5
. If
ENCODER ENABLE is held high continuously, consecutive
words will be encoded without an interframe gap.
ENCODER ENABLE must go low by time
5
(as shown) to
prevent a consecutive word from being encoded. At any time
a low on OUTPUT INHIBIT input will force both bipolar out-
puts to a high state but will not affect the Encoder in any
other way.
To abort the Encoder transmission, a positive pulse must be
applied at MASTER RESET. Any time after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
0
1
2
3
4
5
6
7
N-4
N-3
N-2
N-1
N
DON’T CARE
VALID
DON’T CARE
1ST HALF 2ND HALF
MSB
BIT K-1 BIT K-2 BIT K-3 BIT K-4
BIT 4
BIT 3
BIT 2
BIT 1
PARITY
SYNC
SYNC
MSB
BIT K-1 BIT K-2 BIT K-3 BIT K-4
BIT 4
BIT 3
BIT 2
BIT 1
PARITY
1
2
3
4
5
FIGURE 1. ENCODER
Decoder Operation
To operate the Decoder asynchronously requires a single
clock with a frequency of 12 times the desired data rate
applied at the DECODER CLOCK input. To operate the
Decoder synchronously requires a SYNCHRONOUS
CLOCK at a frequency 2 times the data rate which is syn-
chronized with the data at every high-to-low transition
applied to the SYNCHRONOUS CLK input. The Manchester
II coded data can be presented to the Decoder asynchro-
nously in one of two ways. The BIPOLAR ONE and
BIPOLAR ZERO inputs will accept data from a comparator
sensed transformer coupled bus as specified in Military Spec
1553. The UNIPOLAR DATA input can only accept nonin-
verted Manchester II coded data. (e.g., from BIPOLAR ONE
OUT on an Encoder through an inverter to Unipolar Data
Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized
1
, the type of sync is indicated by a high
level at either COMMAND SYNC or DATA SYNC output. If
the sync character was a command sync the COMMAND
SYNC output will go high
2
and remain high for K SHIFT
CLOCK periods
3
, where K is the number of bits to be
received. If the sync character was a data sync, the DATA
SYNC output will go high. The TAKE DATA output will go
high and remain high
2
-
3
while the Decoder is transmit-
5
FPGA/CPLD
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