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JAN2N3418S

产品描述Transistor
产品类别分立半导体    晶体管   
文件大小442KB,共30页
制造商Aeroflex Metelics / Hi-Rel Components
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JAN2N3418S概述

Transistor

JAN2N3418S规格参数

参数名称属性值
包装说明,
Reach Compliance Codeunknown
最大集电极电流 (IC)3 A
配置Single
最小直流电流增益 (hFE)20
极性/信道类型NPN
最大功率耗散 (Abs)1 W
Base Number Matches1

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The documentation and process conversion measures
necessary to comply with this document shall be
completed by 17 May 2010.
INCH-POUND
MIL-PRF-19500/393J
17 February 2010
SUPERSEDING
MIL-PRF-19500/393H
9 June 2008
PERFORMANCE SPECIFICATION SHEET
* SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON POWER,
TYPES 2N3418, 2N3418S, 2N3418U4, 2N3419, 2N3419S, 2N3419U4, 2N3420, 2N3420S,
2N3420U4, 2N3421, 2N3421S, AND 2N3421U4, JAN, JANTX, JANTXV, JANS, JANSM, JANSD, JANSP,
JANSL, JANSR, JANSF, JANSG, JANSH, JANHCC, JANKCC, JANKCCM, JANKCCD, JANKCCP, JANKCCL,
JANKCCR, JANKCCF, JANKCCG, AND JANKCCH
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1. Scope. This specification covers the performance requirements for NPN, silicon, transistors for use in
medium power switching applications. Four levels of product assurance are provided for each device type, and two
levels of product assurance for die (element evaluation) are provided, as specified in MIL-PRF-19500. RHA level
designators “M”, “D”, “P“, “L”, “R”, “F”, “G”, and “H” are appended to the device prefix to identify devices, which have
passed RHA requirements.
* 1.2. Physical dimensions. See figure 1 (similar to TO-5 for long leaded devices and TO-39 for short leaded
devices), figure 2 for JANHC and JANKC (die), and figure 3 (2N3418U4 through 2N3421U4) dimensions.
*
1.3 Maximum ratings, unless otherwise specified T
A
= +25°C.
Type
P
T
T
A
=
+25°C (1)
W
2N3418, 2N3418S
2N3418U4
2N3419, 2N3419S
2N3419U4
2N3420, 2N3420S
2N3420U4
2N3421, 2N3421S
2N3421U4
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
P
T
T
C
=
+100°C (1)
W
5
15
5
15
5
15
5
15
V
CBO
V
CEO
V
EBO
I
C
I
C
(2)
A dc
5
5
5
5
5
5
5
5
T
STG
and T
J
°C
-65 to
+200
-65 to
+200
-65 to
+200
-65 to
+200
R
θJA
(3)
°C/W
175
175
175
175
175
175
175
175
R
θJC
(3)
°C/W
18
4.5
18
4.5
18
4.5
18
4.5
V dc
85
85
125
125
85
85
125
125
V dc
60
60
80
80
60
60
80
80
V dc
8
8
8
8
8
8
8
8
A dc
3
3
3
3
3
3
3
3
*
*
(1) For derating, see figure 4 through figure 6.
(2) This value applies for t
p
1 ms, duty cycle
50 percent.
(3) For thermal impedance curves see figures 7, 8, and 9.
* Comments, suggestions, or questions on this document should be addressed to Defense Supply Center,
Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to
Semiconductor@dscc.dla.mil.
Since contact information can change, you may want to verify the currency of this
address information using the ASSIST Online database at
https://assist.daps.dla.mil
.
AMSC N/A
FSC 5961

 
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