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HM5316123B Series
131,072-word
×
16-bit Multiport CMOS Video RAM
The HM5316123B is a 2-Mbit multiport video
RAM equipped with a 128-kword
×
16-bit dynamic
RAM and a 256-word
×
16-bit SAM (full-sized
SAM). Its RAM and SAM operate independently
and asynchronously. The HM5316123B has
compatibility with the HM5316123.
Preliminary
E0160H10 (Ver. 1.0)
(Previous ADE-203-266 (Z))
Jun. 14, 2001
Features
• Bidirectional data transfer cycle between RAM
and SAM capability
• Split transfer cycle capability
• Block write mode capability
• Flash write mode capability
• 3 variations of refresh (8 ms/512 cycles)
–RAS-only refresh
–CAS-before-RAS refresh
–Hidden refresh
• TTL compatible
• Multiport organization
Asynchronous and simultaneous operation of
RAM and SAM capability
RAM: 128-kword
×
16-bit
SAM: 256-word
×
16-bit
• Access time
RAM: 70 ns/80 ns/100 ns (max)
SAM: 20 ns/23 ns/25 ns (max)
• Cycle time
RAM: 130 ns/150 ns/180 ns (min)
SAM: 25 ns/28 ns/30 ns (min)
• Low power
Active
RAM: 660 mW/605 mW/550 mW
SAM: 468 mW/413 mW/385 mW
Standby 38.5mW (max)
• Masked-write-transfer cycle capability
• Stopping column feature capability
• Persistent mask capability
• Byte write control capability: 2WE control
• Fast page mode capability
Cycle time: 45ns/50ns/55ns
Power RAM: 688 mW/660 mW/633 mW
• Mask write mode capability
Ordering Information
Type No.
Access time Package
———————————————————————
HM5316123BF-7
70ns
64-pin plastic
——————————————
shrink SOP
HM5316123BF-8
80ns
(FP-64DS)
——————————————
HM5316123BF-10
100ns
———————————————————————
Preliminary: This document contains information on a new
product. Specifications and information contained herein
are subject to change without notice.
Elpida Memory, Inc. is a joint venture DRAM company of NEC corporation and Hitachi, Ltd.
HM5316123B Series
Pin Arrangement
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Pin Description
HM5316123BF Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
CC
DT/DE
V
SS
SI/O0
I/O0
SI/O1
I/O1
V
CC
SI/O2
I/O2
SI/O3
I/O3
V
SS
SI/O4
I/O4
SI/O5
I/O5
V
CC
SI/O6
I/O6
SI/O7
I/O7
V
SS
WEL
WEU
RAS
A8
A7
A6
A5
A4
V
CC
SC
SE
V
SS
SI/O15
I/O15
SI/O14
I/O14
V
CC
SI/O13
I/O13
SI/O12
I/O12
V
SS
SI/O11
I/O11
SI/O10
I/O10
V
CC
SI/O9
I/O9
SI/O8
I/O8
V
SS
DSF1
DSF2
CAS
QSF
A0
A1
A2
A3
V
SS
Symbol
Function
——————————————————————–
A0 – A8
Address inputs
——————————————————————–
I/O0 – I/O15
RAM port data inputs/outputs
——————————————————————–
SI/O0 – SI/O15
SAM port data inputs/outputs
——————————————————————–
RAS
Row address strobe
——————————————————————–
CAS
Column address strobe
——————————————————————–
WEU
Upper byte write enable
——————————————————————–
WEL
Lower byte write enable
——————————————————————–
DT/OE
Date transfer/output enable
——————————————————————–
SC
Serial clock
——————————————————————–
SE
SAM port enable
——————————————————————–
DSF1, DSF2
Special function input flag
——————————————————————–
QSF
Special function output flag
——————————————————————–
VCC
Power Supply
——————————————————————–
VSS
Ground
——————————————————————–
(Top View)
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Preliminary Data Sheet E0160H10
HM5316123B Series
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Block Diagram
A0 – A8
A0 – A7
Column Address
Buffer
A0 – A8
Row Address
Buffer
Refresh
Counter
Row Decoder
Serial Address
Counter
SAM Column Decoder
Sense Amplifier & I/O Bus
Block Write Flash Write
Control
Control
511
Column Decoder
Transfer
Gate
Data
Register
0
255 Memory Array
0
Input Data
Control
Transfer
Gate
Data
Register
Serial Output
Buffer
SAM I/O Bus
Serial Input
Buffer
Address Mask
Register
Mask
Register
Color
Resister
SI/O0 – SI/O15
Input
Buffer
Output
Buffer
Timing Generator
I/O0 – I/O15
QSF
Preliminary Data Sheet E0160H10
RAS
CAS
DT/OE
WEU/WEL
DSF1/DSF2
SC
SE
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HM5316123B Series
Pin Functions
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RAS
(input pin):
RAS
is a basic RAM signal. It is
active in low level and standby in high level. Row
address and signals as shown in table 1 are input at
the falling edge of
RAS.
The input level of these
signals determine the operation cycle of the
HM5316123B.
Table 1. Operation Cycles of the HM5316123B
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Preliminary Data Sheet E0160H10
RAS
CAS
Address
I/On Input
Mnemonic ———————————————— ——————— —————— ——————————
Code
CAS DT/OE WE
DSF1 DSF2
DSF1 DSF2
RAS CAS
RAS
CAS/WE
———————————————————————————————————————————————–
CBRS
0
—
0
1
0
—
0
Stop —
—
—
———————————————————————————————————————————————–
CBRR
0
—
1
0
0
—
0
—
—
—
—
———————————————————————————————————————————————–
CBRN
0
—
1
1
0
—
0
—
—
—
—
———————————————————————————————————————————————–
MWT
1
0
0
0
0
—
0
Row TAP
WN
—
———————————————————————————————————————————————–
MSWT
1
0
0
1
0
—
0
Row TAP
WM
—
———————————————————————————————————————————————–
RT
1
0
1
0
0
—
0
Row TAP
—
—
———————————————————————————————————————————————–
SRT
1
0
1
1
0
—
0
Row TAP
—
—
———————————————————————————————————————————————–
RWM
1
1
0
0
0
0
0
Row Column WM
Input data
———————————————————————————————————————————————–
Register
Mnemonic Write
Pers
———————– No.of
Code
Mask
W.M.
WM
Color
Bndry
Function
———————————————————————————————————————————————–
CBRS
—
—
—
—
Set
CBR refresh with stop resister set
———————————————————————————————————————————————–
CBRR
—
Reset
Reset
—
Reset
CBR refresh with register reset
———————————————————————————————————————————————–
CBRN
—
—
—
—
—
CBR refresh (no reset)
———————————————————————————————————————————————–
MWT
Yes
No
Load/use —
—
Mask write transfer (new/old mask)
Yes
Use
———————————————————————————————————————————————–
MSWT
Yes
No
Load/use —
Use
Masked split write transfer (new/old mask)
Yes
Use
———————————————————————————————————————————————–
RT
—
—
—
—
—
Read transfer
———————————————————————————————————————————————–
SRT
—
—
—
—
Use
Split read transfer
———————————————————————————————————————————————–
RWM
YES
No
Load/use —
—
Road/write (new/old mask)
Yes
Use
———————————————————————————————————————————————–
HM5316123B Series
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Table 1. Operation Cycles of the HM5316123B (cont)
Preliminary Data Sheet E0160H10
Mnemonic
RAS
CAS
Address
I/On Input
————————————————
—————— ——————
—————————–
Code
CAS DT/OE WE
DSF1 DSF2
DSF1 DSF2
RAS CAS
RAS
CAS/WE
———————————————————————————————————————————————–
BWM
1
1
0
0
0
1
0
Row Column WM
Column
Mask
———————————————————————————————————————————————–
RW (No)
1
1
1
0
0
0
0
Row Column —
Input data
———————————————————————————————————————————————–
BW (No)
1
1
1
0
0
1
0
Row Column —
Column
Mask
———————————————————————————————————————————————–
FWM
1
1
0
1
0
—
0
Row —
WM
—
———————————————————————————————————————————————–
LMR and
1
1
1
1
0
0
0
(Row) —
—
Mask
Old Mask Set
Data
———————————————————————————————————————————————–
LCR
1
1
1
1
0
1
0
(Row) —
—
Color
———————————————————————————————————————————————–
Option
0
0
0
0
0
—
0
Mode —
Data
—
———————————————————————————————————————————————–
Register
Mnemonic Write
Pers
———————
No.of
Code
Mask
W.M.
WM
Color
Bndry
Function
———————————————————————————————————————————————–
BWM
Yes
No
Load/use
Block write (new/old mask)
Yes
Use
Use
—
———————————————————————————————————————————————–
RW (No)
No
No
—
—
—
Read/write (no mask)
———————————————————————————————————————————————–
BW (No)
No
No
—
Use
—
Block write (no mask)
———————————————————————————————————————————————–
FWM
Yes
No
Load/use Use
—
Masked flash write (new/old mask)
Yes
Use
———————————————————————————————————————————————–
LMR and
—
Set
Load
—
—
Load mask register and old mask set
Old Mask Set
———————————————————————————————————————————————–
LCR
—
—
—
Load
—
Load color resister set
———————————————————————————————————————————————–
Option
—
—
—
—
—
—
———————————————————————————————————————————————–
Notes: 1. With CBRS, all SAM operations use stop register.
2. After LMR, RWM, BWM, FWM, MWT, and MSWT, use old mask which can be reset by CBRR.
3. DSF2 is fixed low in all operation. (for the addition of operation mode in future)
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