EO
Description
Features
HM534253B Series
1 M VRAM (256-kword
×
4-bit)
E0165H10 (Ver. 1.0)
(Previous ADE-203-204D (Z))
Jul. 6, 2001 (K)
The HM534253B is a 1-Mbit multiport video RAM equipped with a 256-kword
×
4-bit dynamic RAM and a
512-word
×
4-bit SAM (serial access memory). Its RAM and SAM operate independently and
asynchronously. It can transfer data between RAM and SAM. In addition, it has two modes to realize fast
writing in RAM. Block write and flash write modes clear the data of 4-word
×
4-bit and the data of one row
(512-word
×
4-bit) respectively in one cycle of RAM. And the HM534253B makes split transfer cycle
possible by dividing SAM into two split buffers equipped with 256-word
×
4-bit each. This cycle can transfer
data to SAM which is not active, and enables a continuous serial access.
•
Multiport organization
Asynchronous and simultaneous operation of RAM and SAM capability
RAM: 256-kword
×
4-bit
SAM: 512-word
×
4-bit
•
Access time
RAM: 60 ns/70 ns/80 ns/100 ns max
SAM: 20 ns/22 ns/25 ns/25 ns max
•
Cycle time
RAM: 125 ns/135 ns/150 ns/180 ns min
SAM: 25 ns/25 ns/30 ns/30 ns min
•
Low power
Active
RAM: 413 mW max
SAM: 275 mW max
Standby 38.5 mW max
•
High-speed page mode capability
•
Mask write mode capability
•
Bidirectional data transfer cycle between RAM and SAM capability
•
Split transfer cycle capability
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HM534253B Series
•
Block write mode capability
•
Flash write mode capability
•
3 variations of refresh (8 ms/512 cycles)
RAS-only
refresh
CAS-before-RAS
refresh
Hidden refresh
•
TTL compatible
EO
Type No.
HM534253BJ-6
HM534253BJ-7
HM534253BJ-8
HM534253BJ-10
HM534253BZ-6
HM534253BZ-7
HM534253BZ-8
HM534253BZ-10
SC
SI/O0
SI/O1
DT/OE
I/O0
I/O1
WE
NC
RAS
A8
A6
A5
A4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
Ordering Information
Pin Arrangement
HM534253BJ Series
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
SI/O3
SI/O2
SE
I/O3
I/O2
DSF
CAS
QSF
A0
A1
A2
A3
A7
(Top view)
LP
Access Time
60 ns
70 ns
80 ns
100 ns
60 ns
70 ns
80 ns
100 ns
Package
400-mil 28-pin plastic SOJ (CP-28D)
400-mil 28-pin plastic ZIP (ZP-28)
Data Sheet E0165H10
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HM534253BZ Series
I/O2
SE
SI/O3
SC
SI/O1
I/O0
WE
RAS
A6
A4
A7
A2
A0
CAS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
1
3
5
7
9
11
13
15
17
19
21
23
25
27
DSF
I/O3
SI/O2
V
SS
SI/O0
DT/OE
I/O1
NC
A8
A5
V
CC
A3
A1
QSF
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(Bottom view)
HM534253B Series
EO
Pin Description
Pin Name
A0 – A8
I/O0 – I/O3
SI/O0 – SI/O3
RAS
CAS
WE
DT/OE
SC
SE
DSF
QSF
V
CC
V
SS
NC
Function
Address inputs
RAM port data inputs/outputs
SAM port data inputs/outputs
Row address strobe
Column address strobe
Write enable
Data transfer/output enable
Serial clock
SAM port enable
Special function input flag
Special function output flag
Power supply
Ground
No connection
LP
Data Sheet E0165H10
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HM534253B Series
Block Diagram
Sense Amplifier & I/O Bus
Block Write Flash Write
Control
Control
Column Decoder
Memory Array
Input Data
Control
Address Mask
Register
Transfer
Gate
Data
Register
Serial Output
Buffer
Serial Input
Buffer
Mask
Register
Color
Register
SI/O0 – SI/O3
Input
Buffer
Output
Buffer
Timing Generator
I/O0 – I/O3
Data Sheet E0165H10
4
RAS
CAS
DT/OE
WE
DSF
SC
SE
SAM Column Decoder
Transfer
Gate
Data
Register
SAM I/O Bus
EO
A0 – A8
Column Address
Buffer
Row Address
Buffer
Refresh
Counter
Row Decoder
Serial Address
Counter
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HM534253B Series
EO
Pin Functions
Table 1
CAS
L
H
H
H
H
H
H
H
H
H
H
H
DT/OE WE
X
L
L
L
L
L
H
H
H
H
H
H
X
L
L
L
H
H
L
L
L
H
H
H
Note: X: H or L.
RAS
(input pin):
RAS
is a basic RAM signal. It is active in low level and standby in high level. Row
address and signals as shown in table 1 are input at the falling edge of
RAS.
The input level of these signals
determine the operation cycle of the HM534253B.
Operation Cycles of the HM534253B
Input Level At The Falling Edge Of
RAS
SE
X
L
DSF
X
L
L
DSF At The Falling Edge Of
CAS
—
X
X
X
X
X
L
Operation Mode
CBR refresh
Write transfer
Pseudo transfer
Split write transfer
Read transfer
Split read transfer
Read/mask write
Mask block write
Flash write
Read/write
Block write
Color register read/write
CAS
(input pin):
Column address and DSF signals are fetched into chip at the falling edge of
CAS,
which
determines the operation mode of the HM534253B.
CAS
controls output impedance of I/O in RAM.
A0 – A8 (input pins):
Row address is determined by A0 – A8 level at the falling edge of
RAS.
Column
address is determined by A0 – A8 level at the falling edge of
CAS.
In transfer cycles, row address is the
address on the word line which transfers data with SAM data register, and column address is the SAM start
address after transfer.
WE
(input pin):
W E
pin has two functions at the falling edge of
RAS
and after. When
WE
is low at the
falling edge of
RAS,
the HM534253B turns to mask write mode. According to the I/O level at the time, write
on each I/O can be masked. (WE level at the falling edge of
RAS
don’t care in read cycle.) When
WE
is high
at the falling edge of
RAS,
a normal write cycle is executed. After that,
WE
switches read/write cycles as in a
standard DRAM. In a transfer cycle, the direction of transfer is determined by
WE
level at the falling edge of
RAS.
When
WE
is low, data is transferred from SAM to RAM (data is written into RAM), and when
WE
is
high, data is transferred from RAM to SAM (data is read from RAM).
LP
H
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
X
L
H
L
L
H
H
X
Data Sheet E0165H10
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