HANBit
HMF2M32B4VN
FLASH-ROM MODULE 8MByte (2M x 32Bit), 144-Pin SODIMM,
3.3V
Part No. HMF2M32B4VN
GENERAL DESCRIPTION
The HMF2M32B4VN is a high-speed flash read only memory (FROM) module containing 8,388,608 words organized in a
x32bit configuration. The module consists of four 2M x 8bit FROM mounted on a 144-pin, double-sided, FR4-printed circuit
board. Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the
device is similar to reading from 12.0V flash or EPROM devices.
Eight chip enable inputs, (/CS0, /CS1, /CS2, /CS3, /CS4, /CS5, /CS6, CS7) are used to enable the module’s 4 bytes
independently. Outputs enable (/OE) and write enable (/WE) can set the memory input and output.When FROM module is
disable condition the module is becoming power standby mode, system designer can get low -power design. All module
components may be powered from a single +3.3V DC power supply and all inputs and outputs are TTL -compatible.
FEATURES
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Part Identifications
HMF2M32B4VN : 8Mbyte, 144-pin SODIMM, Gold
wAccess
time : 70, 90 and 120ns
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High-density 8MByte design
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High-reliability, low-power design
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Single + 3V
±
0.5V power supply
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Easy memory expansion
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All inputs and outputs are TTL-compatible
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FR4-PCB design
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Low profile 144-pin SODIMM
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Minimum 1,000,000 write/erase cycle
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Sectors erase architecture
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Sector group protection
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Temporary sector group unprotection
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The used device is 2Mx8bit 48Pin TSOP
OPTIONS
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Timing
70ns access
90ns access
120ns access
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Packages
144-pin SODIMM
MARKING
-70
-90
-120
B
,URL: www.hbe.co.kr
REV.02(August,2002)
1
HANBit Electronics Co., Ltd.
HANBit
HMF2M32B4VN
PIN ASSIGNMENT
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
Front
Vss
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
Vss
/CS0
/CS1
V
CC
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
V
CC
DQ12
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Back
Vss
NC
NC
NC
NC
V
CC
NC
NC
NC
NC
Vss
NC(/CS4
)
NC(/CS5
)
V
CC
A3
A4
A5
Vss
NC
NC
NC
NC
V
CC
NC
PIN
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
Frontl
DQ13
DQ14
DQ15
Vss
NC
NC
NC
V
CC
NC
/WE
A13
A14
A15
Vss
A19
A20
V
CC
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
PIN
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Back
NC
NC
NC
Vss
NC
NC
NC
V
CC
NC
/OE
A16
A17
A18
Vss
A21
NC
V
CC
NC
NC
NC
NC
Vss
NC
NC
PIN
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Front
DQ22
DQ23
V
CC
A6
A8
Vss
A9
A10
V
CC
/CS2
/CS3
Vss
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
Vss
NC
V
CC
PIN
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
NC
NC
V
CC
A7
NC
Vss
A12
A11
V
CC
NC(/CS6)
NC(/CS7)
Vss
NC
NC
NC
NC
V
CC
NC
NC
RY_/BY
/RESET
Vss
NC
V
CC
,URL: www.hbe.co.kr
REV.02(August,2002)
2
HANBit Electronics Co., Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
DQ32
DQ 0-DQ31
A0-A20
A21
HMF2M32B4VN
A0
A1-A20
DQ15/A1
A0-19
DQ0-7
/WE
/OE
U1
/CE
/CS0
DQ15/A1
A0-19
/WE
/OE
/CS1
DQ15/A1
A0-19
DQ16-23
/WE
/OE
DQ8-15
U2
/CE
U3
/CE
/CS2
DQ15/A1
A0-19
/
WE
/OE
DQ24-31
/WE
/OE
U4
/CE
/CS3
/RESET
FROM U1 - U8
RY_/BY
FROM U1 - U8
,URL: www.hbe.co.kr
REV.02(August,2002)
3
HANBit Electronics Co., Ltd.
HANBit
TRUTH TABLE
MODE
STANDBY
NOT SELECTED
READ
WRITE or ERASE
NOTE: X means don’t care
/OE
X
H
L
H
/CE
Vcc± 0.3
L
L
L
/WE
X
H
H
L
DQ
HIGH-Z
HIGH-Z
Dout
Din
HMF2M32B4VN
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage with respect to ground all other pins
Voltage with respect to ground Vcc
Storage Temperature
SYMBOL
V
IN,OUT
V
CC
T
STG
RATING
-0.5V to +0.5V
-0.5V to +4.0V
-65oC to +150oC
Operating Temperature
T
A
-55Oc to +125 oC
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Stresses greater than those listed under " Absolute Maximum Ratings" may cause per manent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rat ing conditions for extended
periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Vcc for
±5%
device Supply Voltages
Vcc for
±
10% device Supply Voltages
Ground
SYMBOL
V
CC
Vcc
V
SS
MIN
3.0V
2.7V
0
0
TYP.
MAX
3.6V
3.6V
0
DC AND OPERATING CHARACTERISTICS
(0oC
≤
TA
≤
70 oC ; Vcc = 5V
±
0.5V )
PARAMETER
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Vcc Active Current for Read(1)
Vcc Active Current for Program
or Erase(2)
Vcc Standby Current
Low Vcc Lock-Out Voltage
Notes:
1. The Icc current listed is typically less than 2mA/MHz, with /OE at V
IH
.
2. Icc active while embedded algorithm (program or erase) is in progress
3. Maximum Icc current specifications are tested with Vcc=Vcc max
TEST CONDITIONS
Vcc=Vcc max, V
IN
= GND to Vcc
Vcc=Vcc max, VOUT= GND to Vcc
I
OH
= -2.5mA, Vcc = Vcc min
I
OL
= 12mA, Vcc =Vcc min
/CE = V
IL
, /OE=V
IH
,
/CE = V
IL
, /OE=V
IH
/CE= V
IH
SYMBOL
I
L1
I
L0
0.85*
V
OH
VCC
V
OL
I
CC1
I
CC2
I
CC3
V
LKO
36
80
0.8
2.3
0.45
64
120
20
2.5
V
mA
mA
mA
V
V
MIN
MAX
±1.0
±1.0
UNITS
µA
µA
,URL: www.hbe.co.kr
REV.02(August,2002)
4
HANBit Electronics Co., Ltd.
HANBit
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
MIN.
Sector Erase Time
Byte Programming Time
Chip Programming Time
-
-
-
TYP.
0.7
9
18
MAX.
15
300
54.8
Sec
µs
Sec
UNIT
HMF2M32B4VN
COMMENTS
Excludes 00H programming
prior to erasure
Excludes system-level
overhead
Excludes system-level
overhead
CAPACITANCE
PARAMETER
SYMBOL
C
IN
C
OUT
C
IN2
PARAMETER
DESCRIPTION
Input Capacitance
Output Capacitance
Control Pin Capacitance
TEST SETUP
V
IN
= 0
V
OUT
= 0
V
IN
= 0
TYP.
24
34
30
MAX
30
4812
369
UNIT
pF
pF
pF
Notes
: Test conditions T
A
= 25
o
C, f=1.0 MHz.
AC CHARACTERISTICS
u
Read Only Operations Characteristics
PARAMETER
SYMBOLS
JEDEC
T
AVAV
T
AVQV
T
ELQV
T
GLQV
T
EHQZ
T
GHQZ
T
AXQX
STANDARD
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
QH
Read Cycle Time
Address to Output Delay
Chip Enable to Output Delay
Chip Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
Output Hold Time From Addresses,
/CE or /OE, Whichever Occurs First
/CE = V
IL
/OE = V
IL
/OE = V
IL
Min
Max
Max
Max
Max
Max
Min
Speed Options
DESCRIPTION
TEST SETUP
70R
70
70
70
30
25
125
0
80
80
80
80
30
25
25
0
-90
90
90
90
35
30
30
0
-120
120
120
120
50
30
30
0
ns
ns
ns
ns
ns
ns
ns
UNIT
Notes
: Test Conditions
Output Load : 1TTL gate and Output Load Capacitance 100 pF, in case of 55ns-30pF
Input rise and fall times : 5 ns , In case of 55ns-5ns
Input pulse levels : 0 .45V to 2.4V, In case of 55ns- 0.0V-3.0V
Timing measurement reference level
Input : 0.8V, Incase of 55ns-1.5V
Output : 2.0V, In case of 55ns-1.5V
,URL: www.hbe.co.kr
REV.02(August,2002)
5
HANBit Electronics Co., Ltd.
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