HANBit
HMF2M64F8V
FLASH-ROM MODULE 16MByte (2M x 64-Bit) ,120PIN SMM,3.3V
Part No. HMF2M64F8V
GENERAL DESCRIPTION
The HMF2M64F8V is a high-speed flash read only memory (FROM) module containing 8,388,608 words organized in an
x64bit configuration. The module consists of eight 1M x 16 FROM mounted on a 120-pin, SMM connector FR4-printed circuit
board.
Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the
device is similar to reading from 12.0V flash or EPROM devices.
Output enable (/OE) and write enable (/WE) can set the memory input and output. The host system can detect a program or
erase operation is complete by observing the Ready Pin, or reading the DQ7(Data # Polling) and DQ6(Toggle) status bits.
When FROM module is disable condition the module is becoming power standby mode, system designer can get low -power
design. All module components may be powered from a single + 3.0V DC power supply and all inputs and outputs are LVTTL-
compatible
FEATURES
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Access time : 70, 90 and 120ns
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High-density 16MByte design
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High-reliability, low-power design
w
Single + 3V
±
0.3V power supply
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Easy memory expansion
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Hardware reset pin(RESET#)
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FR4-PCB design
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120-Pin Designed by 60-Pin Fine Pitch Connector P1,P2
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Minimum 1,000,000 write cycle guarantee per sector
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20-year data retention at 125 oC
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Flexible sector architecture
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Embedded algorithms
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Erase suspend / Erase resume
OPTIONS
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Timing
70ns access
90ns access
120ns access
MARKING
-70
-90
-120
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Packages
120-pin SMM
F
URL: www.hbe.co.kr
REV.02(August.2002)
1
HANbit Electronics Co., Ltd.
HANBit
HMF2M64F8V
PIN ASSIGNMENT
P1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
Vcc
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vcc
A1
A2
A3
A4
A5
Vcc
A6
A7
A8
A9
Vcc
PIN
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
A10
A11
A12
A13
A14
Vss
A15
A17
A18
A19
Vss
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
Vcc
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vcc
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vcc
A20
A0
A16
/WE1
/WE2
Vcc
/OE
/RESET
/WE0
/RY_BY
Vcc
P2
PIN
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
Vss
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vss
NC
/BANK0
Vss
Vss
/WE3
Vss
/WE4
/WE5
/WE6
/WE7
Vss
URL: www.hbe.co.kr
REV.02(August.2002)
2
HANbit Electronics Co., Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
DQ0
–
DQ63
A0
–
A20
64
21
A1-A20
A0
/WE0
A(0-19)
DQ15
/WE
/OE
/CE
RY-BY
/RESE
DQ(0-7)
HMF2M64F8V
A(0-
/WE4
DQ(32-
DQ15
/WE
/OE
/
BYTE
/BYTE
U2
/CE
RY-BY
/RESE
U6
A(0-19)
DQ15 DQ(8-15)
/WE1
/WE
/OE
/CE
RY-BY
/BYTE
/
WE5
A(0-19)
DQ(40-
DQ15
/
WE
/
OE
/CE
RY-BY
/RESE
/
BYTE
U3
U7
/
RESE
/WE2
A(0-
19)
DQ15
DQ(16-
/WE
23)
/
BYTE
/OE
/CE
RY-BY
/RESE
/WE6
A(0-19)
DQ15
DQ(48-
/
WE
55)
/BYTE
/
OE
/CE
RY-BY
/RESE
U1
U5
A(0-19)
DQ15
DQ(24-31)
/WE3
/WE
/WE7
/BANK0
/BYTE
/
OE
/BANK0
A(0-19)
DQ15
DQ(56-63)
/
WE
/BYTE
/OE
/
CE
RY-BY
/RESE
U4
/
CE
RY-BY
U8
/
RESE
/OE
RY_/BY
/RESET
URL: www.hbe.co.kr
REV.02(August.2002)
3
HANbit Electronics Co., Ltd.
HANBit
TRUTH TABLE
MODE
STANDBY
NOT SELECTED
READ
WRITE or ERASE
NOTE: X means don’t care
/OE
X
H
L
H
/CE
Vcc± 0.3
L
L
L
/WE
X
H
H
L
DQ
HIGH-Z
HIGH-Z
Dout
Din
HMF2M64F8V
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage with respect to ground all other pins
Voltage with respect to ground Vcc
Storage Temperature
SYMBOL
V
IN,OUT
V
CC
T
STG
RATING
-0.5V to +0.5V
-0.5V to +4.0V
-65oC to +150oC
Operating Temperature
T
A
-55Oc to +125 oC
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Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Vcc for
±5%
device Supply Voltages
Vcc for
±
10% device Supply Voltages
Ground
SYMBOL
V
CC
Vcc
V
SS
MIN
3.0V
2.7V
0
0
TYP.
MAX
3.6V
3.6V
0
DC AND OPERATING CHARACTERISTICS
(0oC
≤
TA
≤
70 oC ; Vcc = 5V
±
0.5V )
PARAMETER
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Vcc Active Current for Read(1)
Vcc Active Current for Program
or Erase(2)
Vcc Standby Current
Low Vcc Lock-Out Voltage
Notes:
1. The Icc current listed is typically less than 2mA/MHz, with /OE at V
IH
.
2. Icc active while embedded algorithm (program or erase) is in progress
3. Maximum Icc current specifications are tested with Vcc=Vcc max
TEST CONDITIONS
Vcc=Vcc max, V
IN
= GND to Vcc
Vcc=Vcc max, VOUT= GND to Vcc
I
OH
= -2.5mA, Vcc = Vcc min
I
OL
= 12mA, Vcc =Vcc min
/CE = V
IL
, /OE=V
IH
,
/CE = V
IL
, /OE=V
IH
/CE= V
IH
SYMBOL
I
L1
I
L0
0.85*
V
OH
VCC
V
OL
I
CC1
I
CC2
I
CC3
V
LKO
72
160
1.6
2.3
0.45
128
240
40
2.5
V
mA
mA
mA
V
V
MIN
MAX
±1.0
±1.0
UNITS
µA
µA
URL: www.hbe.co.kr
REV.02(August.2002)
4
HANbit Electronics Co., Ltd.
HANBit
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
MIN.
Sector Erase Time
Byte Programming Time
Chip Programming Time
-
-
-
TYP.
0.7
9
18
MAX.
15
300
54.8
Sec
µs
Sec
UNIT
HMF2M64F8V
COMMENTS
Excludes 00H programming
prior to erasure
Excludes system-level
overhead
Excludes system-level
overhead
CAPACITANCE
PARAMETER
SYMBOL
C
IN
C
OUT
C
IN2
PARAMETER
DESCRIPTION
Input Capacitance
Output Capacitance
Control Pin Capacitance
TEST SETUP
V
IN
= 0
V
OUT
= 0
V
IN
= 0
TYP.
48
68
60
MAX
60
96
72
UNIT
pF
pF
pF
Notes
: Test conditions T
A
= 25
o
C, f=1.0 MHz.
AC CHARACTERISTICS
u
Read Only Operations Characteristics
PARAMETER
SYMBOLS
JEDEC
T
AVAV
T
AVQV
T
ELQV
T
GLQV
T
EHQZ
T
GHQZ
T
AXQX
STANDARD
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
QH
Read Cycle Time
Address to Output Delay
Chip Enable to Output Delay
Chip Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
Output Hold Time From Addresses,
/CE or /OE, Whichever Occurs First
/CE = V
IL
/OE = V
IL
/OE = V
IL
Min
Max
Max
Max
Max
Max
Min
Speed Options
DESCRIPTION
TEST SETUP
70R
70
70
70
30
25
125
0
80
80
80
80
30
25
25
0
-90
90
90
90
35
30
30
0
-120
120
120
120
50
30
30
0
ns
ns
ns
ns
ns
ns
ns
UNIT
Notes
: Test Conditions
Output Load : 1TTL gate and Output Load Capacitance 100 pF, in case of 55ns-30pF
Input rise and fall times : 5 ns , In case of 55ns-5ns
Input pulse levels : 0 .45V to 2.4V, In case of 55ns- 0.0V-3.0V
Timing measurement reference level
Input : 0.8V, Incase of 55ns-1.5V
Output : 2.0V, In case of 55ns-1.5V
URL: www.hbe.co.kr
REV.02(August.2002)
5
HANbit Electronics Co., Ltd.
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