Integrated
Circuit
Systems, Inc.
ICS85222-01
D
UAL
LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
F
EATURES
•
Two differential HSTL outputs
•
CLK0, CLK1 LVCMOS/LVTTL clock inputs
•
CLK0 and CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 350MHz
•
Part-to-part skew: 375ps (maximum)
•
Propagation delay: 1075ps (maximum)
•
V
OH
: 1.4V (maximum)
•
Full 3.3V and 2.5V operating supply voltage
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS85222-01 is a Dual LVCMOS / LVTTL-
to-Differential HSTL translator and a member of
HiPerClockS™
the HiPerClocks™ family of High Performance
Clock Solutions from ICS. The ICS85222-01 has
two single ended clock inputs. The single ended
clock input accepts LVCMOS or LVTTL input levels and trans-
lates them to HSTL levels. The small outline 8-pin SOIC pack-
age makes this device ideal for applications where space,
high performance and low power are important.
IC
S
B
LOCK
D
IAGRAM
CLK0
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
DD
CLK0
CLK1
GND
CLK1
ICS85222-01
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
85222AM-01
www.icst.com/products/hiperclocks.html
1
REV. A NOVEMBER 15, 2005
Integrated
Circuit
Systems, Inc.
ICS85222-01
D
UAL
LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
Type
Output
Output
Power
Input
Input
Pullup
Pullup
Description
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
LVCMOS / LVTTL clock input.
LVCMOS / LVTTL clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
Name
Q0, nQ0
Q1, nQ1
GN D
CLK1
CLK0
Power
Positive supply pin.
8
V
DD
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
NOTE: Unused output pairs must be terminated.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
85222AM-01
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 15, 2005
Integrated
Circuit
Systems, Inc.
ICS85222-01
D
UAL
LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DD
I
DD
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
35
Units
V
V
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK0, CLK1
CLK0, CLK1
CLK0, CLK1
CLK0, CLK1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 2.625V
V
DD
= 3.465, V
IN
= 0V
V
DD
= 2.625, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
5
Units
V
V
µA
µA
T
ABLE
3C. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
Test Conditions
Minimum
1
0
0
0.6
0.45
Typical
Maximum
1.4
0.4
0.55
1.4
1.4
Units
V
V
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to GND.
85222AM-01
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 15, 2005
Integrated
Circuit
Systems, Inc.
ICS85222-01
D
UAL
LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
Test Conditions
Minimum
700
20% to 80%
ƒ
≤
150MHz
150 < ƒ
≤
250MHz
150
48
46
Typical
Maximum
350
1075
375
800
52
54
Units
MHz
ps
ps
ps
%
%
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
t
sk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
250 < ƒ
≤
350MHz
45
55
%
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
t
sk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ
≤
150MHz
150
48
700
Test Conditions
Minimum
Typical
Maximum
350
1200
475
800
52
Units
MHz
ps
ps
ps
%
150 < ƒ
≤
350MHz
46
54
%
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85222AM-01
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 15, 2005
Integrated
Circuit
Systems, Inc.
ICS85222-01
D
UAL
LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V ± 5%
2.5V ± 5%
V
DD
Qx
SCOPE
V
DD
Qx
SCOPE
HSTL
nQx
HSTL
nQx
GND
GND
0V
0V
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
PART 1
nQx
CLK0,
CLK1
nQ0, nQ1
Q0, Q1
t
PD
V
DD
2
Qx
PART 2
nQy
Qy
tsk(pp)
P
ROPAGATION
D
ELAY
P
ART
-
TO
-P
ART
S
KEW
nQ0, nQ1
80%
Q0, Q1
80%
V
SW I N G
t
PW
t
PERIOD
Clock
Outputs
20%
t
R
t
F
20%
odc =
t
PW
t
PERIOD
x 100%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
85222AM-01
O
UTPUT
R
ISE
/F
ALL
T
IME
REV. A NOVEMBER 15, 2005
www.icst.com/products/hiperclocks.html
5
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