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IDT82V3352概述

SYNCHRONOUS ETHERNET WAN PLL

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SYNCHRONOUS ETHERNET

WAN PLL

IDT82V3352

Version 3

March 23, 2009

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

FEATURES .............................................................................................................................................................................. 7

HIGHLIGHTS.................................................................................................................................................................................................... 7

MAIN FEATURES ............................................................................................................................................................................................ 7

OTHER FEATURES ......................................................................................................................................................................................... 7

APPLICATIONS....................................................................................................................................................................... 7

DESCRIPTION......................................................................................................................................................................... 8

FUNCTIONAL BLOCK DIAGRAM .......................................................................................................................................... 9

1 PIN ASSIGNMENT ........................................................................................................................................................... 10

2 PIN DESCRIPTION .......................................................................................................................................................... 11

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 15

3.1

3.2

3.3

RESET ........................................................................................................................................................................................................... 15

MASTER CLOCK .......................................................................................................................................................................................... 15

INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 16

3.3.1 Input Clocks .................................................................................................................................................................................... 16

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 16

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 17

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 18

3.5.1 Activity Monitoring ......................................................................................................................................................................... 18

3.5.2 Frequency Monitoring ................................................................................................................................................................... 19

3.6 DPLL INPUT CLOCK SELECTION .............................................................................................................................................................. 20

3.6.1 External Fast Selection .................................................................................................................................................................. 20

3.6.2 Forced Selection ............................................................................................................................................................................ 21

3.6.3 Automatic Selection ....................................................................................................................................................................... 21

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 22

3.7.1 DPLL Locking Detection ................................................................................................................................................................ 22

3.7.1.1 Fast Loss .......................................................................................................................................................................... 22

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 22

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 22

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 22

3.7.2 Locking Status ............................................................................................................................................................................... 22

3.7.3 Phase Lock Alarm .......................................................................................................................................................................... 22

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 24

3.8.1 Input Clock Validity ........................................................................................................................................................................ 24

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 24

3.8.2.1 Revertive Switch ............................................................................................................................................................... 24

3.8.2.2 Non-Revertive Switch ....................................................................................................................................................... 24

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 24

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 26

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 26

3.10 DPLL OPERATING MODE ........................................................................................................................................................................... 28

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 28

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 28

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 28

3.10.1.3 Locked Mode .................................................................................................................................................................... 28

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 28

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 28

3.10.1.5 Holdover Mode ................................................................................................................................................................. 28

March 23, 2009

Table of Contents

IDT82V3352

SYNCHRONOUS ETHERNET WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

3.17

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 29

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 29

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 29

3.10.1.5.4 Manual ........................................................................................................................................................... 29

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 29

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 29

DPLL OUTPUT .............................................................................................................................................................................................. 30

3.11.1 PFD Output Limit ............................................................................................................................................................................ 30

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 30

3.11.3 PBO ................................................................................................................................................................................................. 30

3.11.4 Phase Offset Selection .................................................................................................................................................................. 30

3.11.5 Four Paths of T0 DPLL Outputs .................................................................................................................................................... 30

3.11.5.1 T0 Path ............................................................................................................................................................................. 30

T0 / T4 APLL ................................................................................................................................................................................................. 31

OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 31

3.13.1 Output Clocks ................................................................................................................................................................................. 31

3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 34

INTERRUPT SUMMARY ............................................................................................................................................................................... 36

T0 SUMMARY ............................................................................................................................................................................................... 36

POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 37

LINE CARD APPLICATION .......................................................................................................................................................................... 38

4 MICROPROCESSOR INTERFACE .................................................................................................................................. 39

5 JTAG ................................................................................................................................................................................ 41

6 PROGRAMMING INFORMATION .................................................................................................................................... 42

6.1

6.2

REGISTER MAP ............................................................................................................................................................................................ 42

REGISTER DESCRIPTION ........................................................................................................................................................................... 47

6.2.1 Global Control Registers ............................................................................................................................................................... 47

6.2.2 Interrupt Registers ......................................................................................................................................................................... 54

6.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 58

6.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 69

6.2.5 T0 DPLL Input Clock Selection Registers .................................................................................................................................... 80

6.2.6 T0 DPLL State Machine Control Registers .................................................................................................................................. 83

6.2.7 T0 DPLL & APLL Configuration Registers ................................................................................................................................... 85

6.2.8 Output Configuration Registers .................................................................................................................................................... 96

6.2.9 PBO & Phase Offset Control Registers ........................................................................................................................................ 99

6.2.10 Synchronization Configuration Registers ................................................................................................................................. 101

JUNCTION TEMPERATURE ...................................................................................................................................................................... 103

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 103

HEATSINK EVALUATION .......................................................................................................................................................................... 103

7 THERMAL MANAGEMENT ........................................................................................................................................... 103

7.1

7.2

7.3

8.1

8.2

8.3

8 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 104

8.4

8.5

8.6

8.7

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 104

RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 104

I/O SPECIFICATIONS ................................................................................................................................................................................. 105

8.3.1 CMOS Input / Output Port ............................................................................................................................................................ 105

8.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 106

8.3.2.1 PECL Input / Output Port ................................................................................................................................................ 106

8.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 108

JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 109

OUTPUT WANDER GENERATION ............................................................................................................................................................ 112

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 113

OUTPUT CLOCK TIMING ........................................................................................................................................................................... 114

PACKAGE DIMENSIONS.................................................................................................................................................... 120

ORDERING INFORMATION................................................................................................................................................ 125

Table of Contents

March 23, 2009

List of Tables

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Table 44:

Table 45:

Table 46:

Table 47:

Table 48:

Table 49:

Pin Description ............................................................................................................................................................................................. 11

Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 15

Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 16

Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 17

Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 19

Input Clock Selection for T0 Path ................................................................................................................................................................ 20

External Fast Selection ................................................................................................................................................................................ 20

‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 21

Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 21

Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 22

Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 22

Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 23

Conditions of Qualified Input Clocks Available for T0 Selection ................................................................................................................. 24

Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 25

T0 DPLL Operating Mode Control ............................................................................................................................................................... 26

Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 28

Frequency Offset Control in Holdover Mode ............................................................................................................................................... 29

Holdover Frequency Offset Read ................................................................................................................................................................ 29

Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 31

Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs ..................................................................................................................... 31

Outputs on OUT1 & OUT2 if Derived from T0 APLL ................................................................................................................................... 32

Outputs on OUT1 & OUT2 if Derived from T4 APLL ................................................................................................................................... 33

Frame Sync Input Signal Selection .............................................................................................................................................................. 34

Synchronization Control ............................................................................................................................................................................... 34

Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 35

Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 36

Read Timing Characteristics in Serial Mode ................................................................................................................................................ 40

Write Timing Characteristics in Serial Mode ................................................................................................................................................ 40

JTAG Timing Characteristics ....................................................................................................................................................................... 41

Register List and Map .................................................................................................................................................................................. 42

Power Consumption and Maximum Junction Temperature ....................................................................................................................... 103

Thermal Data ............................................................................................................................................................................................. 103

Absolute Maximum Rating ......................................................................................................................................................................... 104

Recommended Operation Conditions ........................................................................................................................................................ 104

CMOS Input Port Electrical Characteristics ............................................................................................................................................... 105

CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 105

CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 105

CMOS Output Port Electrical Characteristics ............................................................................................................................................ 105

PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 107

LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 108

Output Clock Jitter Generation .................................................................................................................................................................. 109

Output Clock Phase Noise ......................................................................................................................................................................... 110

Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 111

Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 111

Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 111

Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 111

T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 111

Input/Output Clock Timing ......................................................................................................................................................................... 113

Output Clock Timing .................................................................................................................................................................................. 115

March 23, 2009

List of Tables

IDT82V3352相似产品对比

	IDT82V3352	82V3352TFG	82V3352EDG	82V3352T
描述	SYNCHRONOUS ETHERNET WAN PLL	SYNCHRONOUS ETHERNET WAN PLL	SYNCHRONOUS ETHERNET WAN PLL	SYNCHRONOUS ETHERNET WAN PLL

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