IDTCV193
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
LP/S CLOCK FOR INTEL BASED
SYSTEMS
FEATURES:
•
•
•
•
•
•
•
IDTCV193
ADVANCE
INFORMATION
Compliant with Intel CK505 Gen II spec
One high precision PLL for CPU, SSC and N programming
One high precision PLL for SRC, SSC and N programming
One high precision PLL for SATA/PCI, and SSC
One high precision PLL for 96MHz/48MHz
Push-pull IOs for differential outputs
Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, byte read/write
• Available in TSSOP package
KEY FEATURES
• Direct CPU and SRC clock frequency programming—write the
Hex number into Byte [16:18], 1MHz stepping.
• Linear and smooth transition for the CPU and SRC frequency
programming.
• SATA PLL source hardware select latch pin, PLL2 or PLL4.
• Internal serial resistor hardware enable latch pin.
• WOL 25MHz support.
OUTPUTS:
•
•
•
•
•
•
•
•
2 - 0.7V differential CPU CLK pair
10 - 0.7V differential SRC CLK pair
1 - CPU_ITP/SRC differential clock pair
1 - SRC0/DOT96 differential clock pair
6 - PCI, 33.3MHz
1 - 48MHz
1 - REF
1 - SATA
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 500ps
• All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II
phase noise requirement.
• SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal
interpair skew = 0 ps
FUNCTIONAL BLOCK DIAGRAM
REF
XTAL_IN
PLL1
SSC
N Programmable
XTAL
Osc Amp
CPU[1:0]
CPU
Output Buffer
Stop Logic
XTAL_OUT
CPU_ITP/SRC8
SDATA
SCLK
SM Bus
Controller
PLL3
SSC
PCI/SATA
SRC CLK
Output Buffer
Stop Logic
PLL4
SSC
N Programmable
SRC1/25MHz/24.576MHz
PCI[4:0], PCIF5
SATA/SRC2
CKPWRGD/PD#
CPU_STOP#
PCI_STOP#
SRC5_EN
ITP_EN
CR_[H:A]#
FSC,B,A
SATA_SEL
SR_ENABLE
Control
Logic
Fixed PLL
PLL2
SRC CLK
Output Buffer
Stop Logic
SRC[7:3], [11:9]
48MHz
48MHz/96MHz
Output BUffer
DOT96/SRC0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2005 Integrated Device Technology, Inc.
IDT CONFIDENTIAL
APRIL 8, 2009
DSC 7165
IDTCV193
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
PCI0/ CR#_A
Vdd_PCI
PCI1/CR#_B
*PCI2/SR_ENABLE
**PCI3/SATA_SEL
PCI4/ SRC5_EN
PCIF5/ ITP_EN
VSS_PCI
Vdd_48
USB 48 / FS_A
Vss_48
Vdd_IO
SRCT0 / DOT96T
SRCC0 / DOT96C
VSS_IO
Vdd_PLL3
SRCT1/25MHz0
SRCC1/25MHz1/24.576MHz
Vss_PLL3
Vdd_PLL3_IO
SRCT2/SATA
SRCC2/SATA
Vss_SRC
SRCT3 / CR#_C
SRCC3 / CR#_D
Vdd_SRC_IO
SRCT4
SRCC4
Vss_SRC
SRCT9
SRCC9
SRCC11/CR#_G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCL
SDA
REF / FS_C / TestSel
Vdd_REF
Xtal_In
Xtal_Out
Vss_REF
FS_B / TestMode
CKPWRGD/PD#
Vdd_CPU
CPUT0
CPUC0
Vss_CPU
CPUT1
CPUC1
Vdd_CPU_IO
Sel_SRC1_25_24.576**
SRCT8 /CPU_ ITPT
SRCC8 /CPU_ ITPC
Vdd_SRC_IO
SRCT7/ CR#_F
SRCC7/ CR#_E
Vss_SRC
SRCT6
SRCC6
Vdd_SRC
PCI_Stop#/ SRCT5
CPU_Stop#/ SRCC5
Vdd_SRC_IO
SRCC10
SRCT10
SRCT11/ CR#_H
* Internal 100k pull high
** Internal 100k pull low
TSSOP
TOP VIEW
IDT CONFIDENTIAL
2
IDTCV193
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Name
PCI0/CR#_A
V
DD
_PCI
PCI1/CR#_B
PCI2/SRC_ENABLE
PCI3/SATA_SEL
PCI4/SRC5_EN
PCIF5/ITP_EN
V
SS
_PCI
V
DD
_48
USB 48/FS_A
V
SS
_48
V
DD
_IO
SRCT0/DOT96T
SRCC0/DOT96C
V
SS
_IO
V
DD
_PLL3
SRCT1/25MHz
SRCC1/25MHz1/24.576MHz
V
SS
_PLL3
V
DD
_PLL3_IO
SATAT/SRCT2
SATAC/SRCC2
V
SS
_SRC
SRCT3/CR#_C
SRCC3/CR#_D
V
DD
_SRC_IO
SRCT4
SRCC4
V
SS
_SRC
SRCT9
SRCC9
SRCC11/CR#_G
SRCT11/CR#_H
SRCT10
SRCC10
V
DD
_SRC_IO
CPU_Stop#/SRCC5
PCI_Stop#/SRCT5
V
DD
_SRC
SRCC6
SRCT6
V
SS
_SRC
Type
I/O
PWR
I/O
I/O
OUT
I/O
I/O
GND
PWR
I/O
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
I/O
I/O
PWR
OUT
OUT
GND
OUT
OUT
I/O
I/O
OUT
OUT
PWR
I/O
I/O
PWR
OUT
OUT
GND
Description
33.33MHz. SRC0, 2 Differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode is selected
by SMBus control register. Default is PCI clock mode.
3.3V
33.33MHz. SRC1, 4 Differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode is selected
by SMBus control register. Default is PCI clock mode.
Power on latch, high, internal 33 ohm resistor enabled. Low, disabled. Afterward 33.33MH
Power on Latch, high, SATA from PLL2. Low, SATA from PLL4 (as SRC clock). Afterward, 33.33MHz
33.33MHz. Pin 37, 38 mode selection. Power on latch, HIGH = SRC5, LOW = CPU and PCI Stop#.
33.33MHz. Pin 46, 47 mode selection. Power on latch, HIGH = CPU_ITP, LOW = SRC8.
GND
3.3V
48MHz, frequency select, power on latch
GND
1.05 ~ 3.3V
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0.
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0.
GND
3.3V
SRC or 25MHz, mode selected by pin 48, Sel_SRC1_25_24.576
SRC or 25Mhz or 24.576MHz, mode selected by pin 48, Sel_SRC1_25_24.576
GND
1.05 ~ 3.3V
Differential output clock
Differential output clock
GND
SRC clock. SRC differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode selected by
SMBus control register. Default is SRC3.
SRC clock. SRC differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode selected by
SMBus control register. Default is SRC3.
1.05 ~ 3.3V
Differential output clock
Differential output clock
GND
Differential output clock
Differential output clock
SRC clock. SRC differential clock output enable, control SRC9, 0 = enable. Mode selected by SMBus control
register. Default is SRC11.
SRC clock. SRC differential clock output enable, control SRC10, 0 = enable. Mode selected by SMBus control
register. Default is SRC11.
Differential output clock
Differential output clock
1.05 ~ 3.3V
CPU stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN.
PCI stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN.
3.3V
Differential output clock
Differential output clock
GND
IDT CONFIDENTIAL
3
IDTCV193
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION, CONTINUED
Pin #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
SRCC7/CR#_E
SRCT7/CR#_F
V
DD
_SRC_IO
SRCC8/CPU_ ITPC
SRCT8/CPU_ ITPT
Sel_SRC1_25_24.576
V
DD
_CPU_IO
CPUC1
CPUT1
V
SS
_CPU
CPUC0
CPUT0
V
DD
_CPU
CKPWRGD/PD#
FS_B/TestMode
V
SS
_REF
XTAL_OUT
XTAL_IN
V
DD
_REF
REF/FS_C/TestSel
SDA
SCL
Type
I/O
I/O
PWR
OUT
OUT
OUT
PWR
OUT
OUT
GND
OUT
OUT
PWR
IN
IN
GND
OUT
IN
PWR
I/O
I/O
IN
Description
SRC clock. SRC differential clock output enable, control SRC6, 0 = enable. Mode selected by SMBus control
register. Default is SRC7.
SRC clock. SRC differential clock output enable, control SRC8, 0 = enable. Mode selected by SMBus control
register. Default is SRC7.
1.05 ~ 3.3V
SRC clock. CPU clock. Mode selected by pin7.
SRC clock. CPU clock. Mode selected by pin7.
Power on latch, Select pin 17, 18 Mode, see pin 48 Function Table.
1.05 ~ 3.3V
Differential output clock
Differential output clock
GND
Differential output clock
Differential output clock
3.3V
CKPWRGD power good, active LOW, used to latch FSA,B,C, ITP_EN, TME, and SRC5_EN , active HIGH.
After, becomes power down, LOW active.
Frequency Select at CKPWRGD assertion. Test Mode selection, see TEST_MODE selection table.q
GND
XTAL out
XTAL in
3.3V
14.318MHz. Frequency Select at CKPWRGD assertion. Selects test mode if pulled above 2V at CKPWRGD
assertion.
SMBus data
SMBus clock
TEST MODE SELECTION
(1)
Test_Mode
1
0
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
If TEST_SEL sampled above 2V at CKPWRGD active LOW
PCI/F
REF/N
Hi-Z
REF
REF
Hi-Z
DOT_96/DOT_SSC
REF/N
Hi-Z
USB
REF/N
Hi-Z
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, with V
IH
_FS and V
IL
_FS thresholds.
FREQUENCY SELECTION
FSC, B, A
101
001
011
010
000
100
110
111
CPU
100
133
166
200
266
333
400
Reserve
SRC[7:0]
100
100
100
100
100
100
100
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
4
USB
48
48
48
48
48
48
48
48
DOT
96
96
96
96
96
96
96
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
IDT CONFIDENTIAL
IDTCV193
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
SEL_SRC1_25_24.576 (PIN 48) VOLTAGE DECODING TABLE
state
Low
Mid
High
Min
0V
1.3V
2.4V
Typ
0.55V
1.65V
2.75V
Max
0.9V
2V
VDD
SR_ENABLE TABLE
SR_ENABLE
0
1 (default)
Need external 33 ohm serial resistor, Byte19 bit7 = 0
Enable 33 ohm internal serial resistor, Byte19 bit7 = 1
SEL_SRC1_25_24.576 FUNCTION TABLE
Sel_SRC1_25_24.576
(pin48 )
Low
CPU
PLL1
PCI
PLL4
Pin 17
25MHz,
PLL3
(SS off)
SRCT1
25MHz
PLL2
Pin 18
25MHz
PLL3
(SS off)
SRCC1
SRC
48/96
PLL4 down PLL2, fixed
Mid
High
PLL1
PLL1
PLL4
PLL4
PLL4 down PLL2, fixed
24.576MHz PLL4 down PLL2, fixed
PLL3
(SS off)
SATA_SEL TABLE
SATA_SEL
0
1
SRC2/SATA
PLL4 (SRC PLL, SSC)
PLL2 (48/96 PLL)
DEVICE ID TABLE
ID3,ID2,ID1,ID0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CK505 56 pin TSSOP
CK505 64 pin TSSOP
48 pin QFN
56 pin QFN
64 pin QFN
72 pin QFN
48 pin SSOP
56 pin SSOP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Comments
CK505 YC
CK505 YC
CK505 YC
CK505 YC
CK505 YC
CK505 YC
CK505 YC
CK505 YC
CK505 Derivative (non YC)
IO_VOUT [2:0] TABLE
000
001
010
011
100
101
110
111
0.3V
0.4V
0.5V
0.6V
0.7V
0.8V
0.9V
1V
IDT CONFIDENTIAL
5
51单片机
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