PCF85102C-2
256
×
8-bit CMOS EEPROM with I
2
C-bus interface
Rev. 04 — 22 October 2004
Product data
1. Description
The PCF85102C-2 is a floating gate Electrically Erasable Programmable Read Only
Memory (EEPROM) with 2 kbits (256
×
8-bit) non-volatile storage. By using an
internal redundant storage code, it is fault tolerant to single bit errors. This feature
dramatically increases the reliability compared to conventional EEPROMs. Power
consumption is low due to the full CMOS technology used. The programming voltage
is generated on-chip, using a voltage multiplier.
Data bytes are received and transmitted via the serial I
2
C-bus. Up to eight
PCF85102C-2 devices may be connected to the I
2
C-bus. Chip select is accomplished
by three address inputs (A0, A1 and A2).
2. Features
s
Low power CMOS:
x
2.0 mA maximum operating current
x
maximum standby current 10
µA
(at 6.0 V), typical 4
µA
s
Non-volatile storage of 2 kbits organized as 256
×
8-bit
s
Single supply with full operation down to 2.5 V
s
On-chip voltage multiplier
s
Serial input/output I
2
C-bus
s
Write operations:
x
byte write mode
x
8-byte page write mode (minimizes total write time per byte)
s
Read operations:
x
sequential read
x
random read
s
Internal timer for writing (no external components)
s
Internal power-on reset
s
0 kHz to 100 kHz clock frequency
s
High reliability by using a redundant storage code
s
Endurance: 1,000,000 Erase/Write (E/W) cycles at T
amb
= 22
°C
s
10 years non-volatile data retention time
s
Pin and address compatible to: PCF8570, PCF8571, PCF8572, PCA8581,
PCF8582
s
Pin compatible (with a different address) to PCF85103
s
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Philips Semiconductors
PCF85102C-2
256
×
8-bit CMOS EEPROM with I
2
C-bus interface
s
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
s
Offered in DIP8 and SO8 packages.
3. Quick reference data
Table 1:
Symbol
V
DD
I
DDR
Quick reference data
Parameter
supply voltage
supply current read
f
SCL
= 100 kHz
V
DD
= 2.5 V
V
DD
= 6 V
I
DDW
supply current E/W
f
SCL
= 100 kHz
V
DD
= 2.5 V
V
DD
= 6 V
I
DD(stb)
standby supply current
V
DD
= 2.5 V
V
DD
= 6 V
-
-
-
-
-
-
-
-
0.6
2.0
3.5
10
mA
mA
µA
µA
-
-
-
-
60
200
µA
µA
Conditions
Min
2.5
Typ
-
Max
6.0
Unit
V
4. Ordering information
Table 2:
Ordering information
Package
Name
PCF85102C-2P/03
PCF85102C-2T/03
DIP8
SO8
Description
plastic dual in-line package; 8 leads (300 mil)
plastic small outline package 8 leads (straight);
body width 3.9 mm
Version
SOT97-1
SOT96-1
Type number
4.1 Ordering options
Table 3:
Ordering options
Topside mark
PCF85102C2
85102C2
Type number
PCF85102C-2P/03
PCF85102C-2T/03
9397 750 14216
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 22 October 2004
2 of 20
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Product data
Rev. 04 — 22 October 2004
A2
A1
A0
3
2
1
VDD
8
4
002aaa247
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14216
5. Block diagram
Philips Semiconductors
PCF85102C-2
SCL
SDA
6
5
n
INPUT
FILTER
I
2
C-BUS CONTROL LOGIC
BYTE
COUNTER
3
ADDRESS
SWITCH
SHIFT
REGISTER
BYTE
LATCH
(8 bytes)
ADDRESS
POINTER
ADDRESS
HIGH
REGISTER
SEQUENCER
DIVIDER
( 128)
8
EEPROM
4
EE
CONTROL
256
×
8-bit CMOS EEPROM with I
2
C-bus interface
TEST MODE DECODER
TIMER
( 16)
POWER-ON-RESET
OSCILLATOR
PCF85102C-2
VSS
3 of 20
Fig 1. Block diagram.
Philips Semiconductors
PCF85102C-2
256
×
8-bit CMOS EEPROM with I
2
C-bus interface
6. Pinning information
6.1 Pinning
A0
1
PCF85102C-2
8 V DD
7
6
5
N.C.
SCL
SDA
A1 2
A2 3
VSS 4
002aaa248
Fig 2. Pin configuration.
6.2 Pin description
Table 4:
Symbol
A0
A1
A2
V
SS
SDA
SCL
N.C.
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
Description
address input 0
address input 1
address input 2
negative supply voltage
serial data input/output (I
2
C-bus)
serial clock input (I
2
C-bus)
no connect
positive supply voltage
7. Device addressing
Table 5:
Selection
Bit
Device
[1]
Device address code
Device code
b7
[1]
1
b6
0
b5
1
b4
0
b3
A2
Chip Enable
b2
A1
b1
A0
R/W
b0
R/W
The Most Significant Bit (MSB) ‘b7’ is sent first.
A2, A1, A0 are hardware selectable pins.
A system could have up to eight PCF85102C-2 devices on the same I
2
C-bus,
equivalent to a 16 kbit EEPROM or 8 pages of 256 bytes of memory.
The eight addresses are defined by the state of the A0, A1, A2 inputs (logic level ‘1’
when connected to V
DD
, logic level ‘0’ when connected to GND).
Figure 3
shows the
various address combinations.
9397 750 14216
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 22 October 2004
4 of 20
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