3.3V supply voltage available (contact factory for 5
volt versions)
Small circuit board footprint (8-pin 0.150″ SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
•
•
•
•
•
The FS6205 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
An on-chip voltage-controlled crystal oscillator (VCXO)
permits the reference frequency (or output frequency) to
be tuned to match other frequencies present in the sys-
tem.
Phase-locked loops are used to generate precise output /
reference frequency ratios. See Table 1 for information
on the frequency ratios programmed into each version of
the FS6205.
Table 1: Version Information
Figure 1: Pin Configuration
XIN
VDD
XTUNE
VSS
1
8
DEVICE
VDD
(nom)
F
REF
(MHz)
FS
MS
CLK
(MHz)
27.000
(REF * 2)
74.175824175…
(REF * 500 / 91)
27.027
(REF * 2)
74.580835443…
(REF * 436 / 79)
XOUT
MS
FS6205-01
3.3
0
13.500
0
1
13.5135
1
0
1
0
1
FS6205
2
3
4
7
6
5
FS
CLK
8-pin (0.150″) SOIC
NOTE: Contact AMI for custom versions
Figure 2: Block Diagram
XIN
VCXO
XOUT
MUX
XTUNE
PLL B
CLK
PLL A
FS
MS
FS6205
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ISO9001
2.28.02
FS6205
VCXO Clock Generator IC
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
1
2
3
4
5
6
7
8
TYPE
AI
P
AI
P
DO
DI
DI
U
U
NAME
XIN
VDD
XTUNE
VSS
CLK
FS
MS
XOUT
VCXO Crystal Feedback
Power Supply (+3.3V nominal)
VCXO Tune
Ground
Clock Output
DESCRIPTION
Frequency Select Input (changes PLL Frequencies)
Multiplexer Select Input (chooses PLL A or PLL B)
VCXO Crystal Drive
AO
3.0
3.1
Functional Block Description
Phase-Locked Loops (PLL)
A simple formula to obtain the pulling capability of a
crystal oscillator is:
6
C
1
×
(
C
L
2
−
C
L
1
)
×
10
∆
f
(
ppm
)
=
2
×
(
C
0
+
C
L
2
)
×
(
C
0
+
C
L
1
)
The on-chip PLLs are a standard frequency- and phase-
locked loop architecture. The PLL multiplies the reference
oscillator to the desired frequency by a ratio of integers.
The frequency multiplication is exactly that specified by
the integer ratios.
3.2
Voltage-Controlled Crystal
Oscillator (VCXO)
where C
L1
and C
L2
are the two extremes of the applied
load capacitance.
EXAMPLE: A crystal with the following parameters is
used. With C
1
= 0.02pF, C
0
= 5pF, C
L1
= 13pF, and C
L2
=
35pF, the tuning range between extreme settings of
XTUNE voltage is:
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6205 system components.
Loading capacitance for the crystal is internal to the
FS6205. No external components (other than the crystal
resonator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin. The
total change (from one extreme to the other) in effective
loading capacitance is 12pF nominal (i.e from 35pF to
13pF).
“Pulling” of the crystal oscillation frequency, is accom-
plished by altering the effective load capacitance pre-
sented to the crystal by the oscillator circuit. The actual
amount that changing the load capacitance alters the os-
cillator frequency will be dependent on the characteristics
of the crystal as well as the oscillator circuit itself.
Specifically, the motional capacitance of the crystal (usu-
ally referred to by crystal manufacturers as C
1
), the static
capacitance of the crystal (C
0
), and the load capacitance
(C
L
) of the oscillator determine the “warping” or “pulling”
capability of the crystal in the oscillator circuit.
2
0
.
02
×
(
35
−
13
)
×
106
∆
f
=
≈
306
ppm
.
2
×
(
5
+
35
)
×
(
5
+
13
)
250
200
150
100
Deviation - ppm
50
0
0
-50
-100
-150
-200
-250
V(XTUNE) - volts
0.5
1
1.5
2
2.5
3
3.5
Figure 3 - Typical VCXO Characteristic
ISO9001
2.28.02
FS6205
VCXO Clock Generator IC
4.0
Electrical Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
Supply Voltage (V
SS
= ground)
Input Voltage, dc
Output Voltage, dc
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Storage Temperature Range (non-condensing)
Ambient Temperature Range, Under Bias
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
V
DD
V
I
V
O
I
IK
I
OK
T
S
T
A
T
J
MIN.
V
SS
-0.5
V
SS
-0.5
V
SS
-0.5
-50
-50
-65
-55
MAX.
7
V
DD
+0.5
V
DD
+0.5
50
50
150
125
125
260
2
UNITS
V
V
V
mA
mA
°C
°C
°C
°C
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 4: Operating Conditions
PARAMETER
Supply Voltage (3.3 volt system)
Ambient Operating Temperature Range
SYMBOL
V
DD
T
A
CONDITIONS/DESCRIPTION
MIN.
3.0
0
TYP.
3.3
MAX.
3.6
70
UNITS
V
°C
3
ISO9001
2.28.02
FS6205
VCXO Clock Generator IC
Table 5: DC Electrical Specifications
Unless otherwise stated, V
DD
= 3.3V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
Overall
Supply Current, Dynamic, with Loaded
Outputs
Clock Outputs (CLKx)
High-Level Output Source Current *
Low-Level Output Sink Current *
Output Impedance *
Short Circuit Source Current *
Short Circuit Sink Current *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
I
DD
f
XTAL
= 13.5MHz; C
L
= 10pF, V
DD
= 3.3V
12
mA
I
OH
I
OL
z
OH
z
OL
I
OSH
I
OSL
V
O
= 2.0V
V
O
= 0.4V
V
O
= 0.5V
DD
; output driving high
V
O
= 0.5V
DD
; output driving low
V
O
= 0V; shorted for 30s, max.
V
O
= 3.3V; shorted for 30s, max.
-40
17
25
25
-55
55
mA
mA
Ω
mA
mA
4
ISO9001
2.28.02
FS6205
VCXO Clock Generator IC
Table 6: AC Timing Specifications
Unless otherwise stated, V
DD
= 3.3V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ from typical.
PARAMETER
Overall
Synthesis Error
Crystal Oscillator
Center Frequency Tuning Volt-
age
Center Frequency Crystal
Loading Capacitance
Crystal Drive Level
Clock Output (CLK)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Long Term (σ
y
(τ)) *
Jitter, Long Term (σ
y
(τ)) *
Rise Time *
Fall Time *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
(unless otherwise noted in Frequency Table)
0
ppm
V
CENTER
For crystal with specified C
L(xtal)
As seen by a crystal connected to XIN and XOUT
(@V
XTUNE
=V
CENTER
). Crystal loading capacitance at
nominal center frequency should be specified for this
value.
R
XTAL
=20Ω;
1.4
V
C
L(xtal)
20
200
pF
uW
Ratio of high pulse width (as measured from rising edge to next falling
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