Generates clocks required for Intel Pentium II based
systems, including:
Four enabled 2.5V 100MHz or 66MHz CPU sys-
tem bus clock outputs
Seven enabled 3.3V PCI bus clocks and one
free-running PCI clock
Three 3.3V REF clocks at 14.318MHz
Two 2.5V APIC clocks at 14.318MHz for APIC
bus timing
Two 3.3V 48MHz clocks for 4x Universal Serial
Bus (USB) timing
The FS6251-01 is a CMOS clock generator IC designed
for high-speed motherboard applications. Two different
frequencies can be selected for the CPU and PCI clocks
via two SEL pins. Glitch-free stop clock control of the
CPU and PCI clocks is provided. A low current power-
down mode is available for mobile applications. Separate
clock buffers provide for a 2.5V voltage range on the
CPU_0:3 and APIC_0:1 clocks.
Figure 2: Pin Configuration (FS6251)
CPU_STOP#
PCI_STOP#
PWR_DWN#
(2.5V outputs)
(reserved)
APIC_0
APIC_1
VDD_R
VDD_C
VDD_C
VDD_A
VSS_C
CPU_0
CPU_1
CPU_2
CPU_3
VSS_A
REF_2
VSS_C
SS_EN#
SEL_0
Non-linear spread spectrum modulation (-0.5% at
31.5kHz)
Selectable 100MHz or 66MHz system bus clock
Supports Intel Test Mode and tristate output control
to facilitate board testing
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
23
SEL_1
48M_1
VDD
VSS
FS6251-01
REF_0
REF_1
VSS_R
48M_0
Separate CPU-enable, PCI-enable and power-down
inputs with glitch-free stop clock controls on all clocks
for clock control and power management
All inputs and 3.3V outputs are LVTTL-compatible
48-pin SSOP
Figure 2: Pin Configuration (FS6252)
CPU_STOP#
PCI_STOP#
(2.5V outputs)
VDD_R
VDD_C
VSS_R
VSS_C
CPU_0
CPU_1
REF_2
VDD
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
SEL
Figure 1: Block Diagram (FS6251)
VDD_R
XIN
Crystal
Oscillator
XOUT
CPU_STOP#
REF_0:2
VSS_R
VDD_A
FS6252-01
10
11
12
13
PCI_2
PCI_3
PCI_4
PCI_1
PCI_5
VSS_P
VDD
VDD_P
VSS_A
VDD_C
CPU_0:3
SEL_0:1
PLL
VSS_C
28-pin SSOP, SOIC
(2.5V outputs)
VDD_P
Table 1: CPU/PCI Frequency Selection
SEL_100/66#
0
0
0
0
1
1
1
1
SEL_1
0
0
1
1
0
0
1
1
SEL_0
0
1
0
1
0
1
0
1
CPU (MHz)
tristate
70
73.33
66.67
XIN/2
105
110
100
PCI (MHz)
tristate
35
36.67
33.33
XIN/6
35
36.67
33.33
SEL_100/66#
PCI_STOP#
SS_EN#
PLL
PWR_DWN#
÷2 or
÷3
delay
PCI_F
PCI_1:7
VSS_P
VDD_U
÷2
48M_0:1
VSS_U
FS6251-01
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Spread spectrum modulation is licensed under US Patent No. 5488627,
Lexmark International, Inc. American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
,62
VDD_P
VSS_P
PCI_F
XOUT
VSS
XIN
APIC_0:1
14
1
2
3
4
5
6
7
8
9
15
SEL_100/66#
PWR_DWN#
•
VDD_U
VDD_P
VDD_P
VSS_U
VSS_P
VSS_P
VSS_P
PCI_F
XOUT
Synchronous clocks skew-matched to <175ps on
CPU and APIC buffers and <250ps on PCI buffers
10
11
12
13
14
15
16
17
18
19
20
21
22
PCI_2
PCI_3
PCI_4
PCI_5
PCI_6
PCI_1
PCI_7
VDD
VSS
XIN
24
1
2
3
4
5
6
7
8
9
25
SEL_100/66#
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Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
(FS6251)
22, 23
35, 36, 39, 40
30
44, 45
8, 10, 11, 13,
14, 16, 17
7
31
29
1, 2, 47
26, 27
25
28
19, 33
46
37, 41
9, 15
48
21
20, 32
43
34, 38
6, 12, 18
3
24
4
5
42
PIN
(FS6252)
-
23, 24
18
-
5, 7, 8, 9
4
19
17
26
16
15
-
13, 21
-
25
9, 12
27
-
14, 20
-
22
3, 12
28
-
1
2
-
TYPE
DO
DO
DI
U
DO
DO
DO
DI
U
DI
U
DO
DI
U
DI
DI
U
P
P
P
P
P
P
P
P
P
P
P
P
AI
AO
-
NAME
48M_0:1
CPU_0:3
CPU_STOP#
APIC_0:1
PCI_1:7
PCI_F
PCI_STOP#
PWR_DWN#
REF_0:2
SEL_0:1
SEL_100/66#
SS_EN#
VDD
VDD_A
VDD_C
VDD_P
VDD_R
VDD_U
VSS
VSS_A
VSS_C
VSS_P
VSS_R
VSS_U
XIN
XOUT
(reserved)
DESCRIPTION
Two 48MHz clock outputs for Universal Serial Bus (USB) timing
Four low-skew (<175ps @ 1.25V) 2.5V to 3.3V CPU clock outputs for host
frequencies. (Two copies of the CPU clock are available in FS6252 version)
CPU_0:3 clock output enable. Asynchronous, active-low disable stops all
CPU clocks in the low state.
Two buffered low-skew (<175ps @ 1.25V) 2.5V/3.3V outputs of the
1. Introduction
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