Two-Way/Four Way Motherboard Clock Generator/Buffer IC
September 2000
1.0
•
Features
Figure 1: Block Diagram
XIN
XOUT
ISEL_0:1
IREF
÷1
÷2
PWR_DWN#
÷3
SS_EN#
SEL133/100#
SEL_A:B
APICON
÷6
VDD_A
Generates the Host and Memory clocks required for
2-way and 4-way multi-processor (MP) clock-
partitioned platforms, including:
M
Six differential current-mode Host clock pairs
M
Two 3.3V Memory Reference clocks
M
66.67MHz and 14.318MHz 3.3V Reference
clocks for the FS6159 device
M
Three optional 33.3MHz 1.8V APIC clocks
Control of current-mode Host clocks via IREF current
programming pin and ISEL_0:1 current multiplier pins
Optional APIC clocks enabled via APICON input
(see Table 5 for Pins 21-23 configuration)
Host clock frequency selection via the SEL_A,
SEL_B, and SEL133/100# pins
Active-low PWR_DWN# signal allows one complete
clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLL, and disables outputs
Spread-spectrum modulation (-0.5% at 31.5kHz) of
Host, Memory, APIC, and 66MHz Reference clocks,
enabled via SS_EN# input
Supports test mode and tristate output control to fa-
cilitate board testing
Available in a 48-pin SSOP and TSSOP
Crystal
Oscillator
adjust
VDD_R
14REF
VSS_R
VDD_H
HOST_P1:6
HOST_N1:6
VSS_H
VDD_66
•
•
•
•
66REF
PLL
Control
÷4
VSS_66
VDD_M
÷4
MREF_P
MREF_N
VSS_M
APIC_0:2
•
FS6158
÷8
VSS_A
optional
•
•
Figure 2: Pin Configuration
VSS_R 1
14REF 2
VDD_R 3
XIN 4
XOUT 5
48 VDD_R
47 VSS / APICON
46 VDD_H
45 HOST_P1
44 HOST_N1
43 VSS_H
42 HOST_P2
41 HOST_N2
40 VDD_H
39 HOST_P3
38 HOST_N3
37 VSS_H
36 HOST_P4
35 HOST_N4
34 VDD_H
33 HOST_P5
32 HOST_N5
31 VSS_H
30 HOST_P6
29 HOST_N6
28 VDD_H
27 IREF
26 VSS_I
25 VDD_I
Pair 1
Table 1: Clock Parameters
CLOCK
GROUP
HOST_P
HOST_N
MREF_P
MREF_N
66REF
14REF
APIC
(optional)
#
PINS
6
6
1
1
1
1
3
3.3V
VDD_H
SUPPLY
VOLTAGE
SUPPLY
GROUP
FREQ.
(MHz)
133.33
100.00
66.67
50.00
66.67
14.318
33.33
PHASE
0°
180°
0°
180°
0°
0°
0°
SKEW
(MAX)
100ps
Pair to
Pair
-
-
-
-
VSS_R 6
VDD_M 7
MREF_P 8
MREF_N 9
VSS_M 10
VDD 11
VSS 12
VDD_66 13
66REF 14
VSS_66 15
SEL133/100# 16
ISEL_0 17
ISEL_1 18
VDD_A 19
VSS_A 20
SEL_A / APIC_0 21
SEL_B / APIC_1 22
SS_EN# / APIC_2 23
PWR_DWN# 24
Pair 2
Pair 3
FS6158-01
Pair 4
3.3V
3.3V
3.3V
1.8V
VDD_M
VDD_66
VDD_R
VDD_A
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
Pair 5
Pair 6
ISO9001
9.18.00
IntWBY
FS6158-01
Two-Way/Four Way Motherboard Clock Generator/Buffer IC
AMERICAN MICROSYSTEMS, INC.
September 2000
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
47
21
TYPE
DI
DIO
NAME
APICON
APIC_0
SEL_A
APIC_1
DESCRIPTION
Enables (logic-high) or disables (logic-low) the optional 1.8V APIC clocks
One of three optional APIC clocks, enabled or disabled by APICON
One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
One of three optional APIC clocks, enabled or disabled by APICON
One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
One of three optional APIC clocks, enabled or disabled by APICON
Active-low spread spectrum enable turns on spread spectrum modulation of PLL clocks. Input
levels are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
One 14.318MHz clock output, provided as a reference clock to the companion clock device
One 66.67MHz clock output, provided as a reference clock to the companion clock device
A fixed precision resistor from this pin to ground provides a reference current used for the
differential current-mode HOST clock outputs
The logic setting on these two pins selects the multiplying factor of the IREF reference current
for the HOST pair outputs
Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1
Host clock pair #2; one of six pairs of current-steering differential current-mode outputs
Host clock pair #3; one of six pairs of current-steering differential current-mode outputs
Host clock pair #4; one of six pairs of current-steering differential current-mode outputs
Host clock pair #5; one of six pairs of current-steering differential current-mode outputs
Host clock pair #6; one of six pairs of current-steering differential current-mode outputs
One clock in a pair of outputs provided as a reference clock to a memory clock driver
One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver
Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.
Selects 133MHz or 100MHz Host clock frequency
3.3V core power supply
1.8V power supply for optional APIC clocks or a 3.3V supply to pins 21-23
3.3V power supply for 66REF clock output
3.3V power supply for the differential HOST clock outputs
3.3V power supply for IREF current reference input
3.3V power supply for MREF clock outputs
3.3V power supply for the 14REF clock output and the crystal oscillator
Core Ground
Ground for the 66REF clock output
Ground for the APIC clock outputs
Ground for the differential HOST clock outputs
Ground for IREF current reference input
Ground for the MREF clock outputs
Ground for the 14REF clock output and the crystal oscillator
14.318MHz crystal oscillator input
14.318MHz crystal oscillator output
SUPPLY
VDD_R
VDD_A
VDD_A,
VDD_H
VDD_A
VDD_A,
VDD_H
VDD_A
VDD_A,
VDD_H
VDD_R
VDD_66
VDD_I
VDD_66
VDD_H
VDD_H
VDD_H
VDD_H
VDD_H
VDD_H
VDD_M
VDD_M
VDD_I
VDD_66
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD_R
VDD_R
9.18.00
22
DIO
SEL_B
APIC_2
23
2
14
27
17, 18
45, 44
42, 41
39, 38
36, 35
33, 32
30, 29
8
9
24
16
11
19
13
28, 34, 40, 46
25
7
3, 48
12
15
20
31, 37, 43
26
10
1, 6
4
5
DIO
DO
DO
AI
DI
AO
AO
AO
AO
AO
AO
DO
DO
DI
DI
P
P
P
P
P
P
P
P
P
P
P
P
P
AI
AO
SS_EN#
14REF
66REF
IREF
ISEL_0
ISEL_1
HOST_P1
HOST_N1
HOST_P2
HOST_N2
HOST_P3
HOST_N3
HOST_P4
HOST_N4
HOST_P5
HOST_N5
HOST_P6
HOST_N6
MREF_P
MREF_N
PWR_DWN#
SEL133/100#
VDD
VDD_A
VDD_66
VDD_H
VDD_I
VDD_M
VDD_R
VSS
VSS_66
VSS_A
VSS_H
VSS_I
VSS_M
VSS_R
XIN
XOUT
ISO9001
2
FS6158
-01
AMERICAN MICROSYSTEMS, INC.
Two-Way/Four Way Motherboard Clock Generator/Buffer IC
September 2000
2.0
Programming Information
Table 3: Function/Clock Enable Configuration
CONTROL INPUTS
(2)
PWR_DWN#
1
1
1
1
1
1
1
1
0
1.
CLOCK OUTPUTS (MHz)
SEL_B
0
1
0
1
0
1
0
1
X
HOST_P1:6
100.00
100.00
reserved
tristate
133.33
reserved
reserved
XIN÷2
2× IREF
HOST_N1:6
100.00
100.00
reserved
tristate
133.33
reserved
reserved
XIN÷2
tristate
MREF_P,
MREF_N
50.00
low
(1)
reserved
tristate
66.67
reserved
reserved
XIN÷4
low
66REF
66.67
low
(1)
reserved
tristate
66.67
reserved
reserved
XIN÷4
low
APIC_0:2
(optional)
33.33
low
(1)
reserved
tristate
33.33
reserved
reserved
XIN÷8
low
14REF
14.318
low
(1)
reserved
tristate
14.318
reserved
reserved
XIN
low
SEL133/100#
0
0
0
0
1
1
1
1
X
SEL_A
0
0
1
1
0
0
1
1
X
Certain clock outputs may be disabled through a combination of SEL_A, SEL_B, and SEL133/100# logic states as defined in Table 3. Enabled clocks will continue to run while disabled clocks
are stopped low. Note that if clocks are disabled while active, glitches may occur.
Table 4: Synthesis Error
CLOCK
HOST_P1:6,
HOST_N1:6
MREF_P,
MREF_N
66REF
APIC_0:2
1.
2.
3.0
ACTUAL
(MHz)
99.9963
133.3072
49.9982
66.6536
66.6642
33.3321
DEVIATION
(ppm)
-36.657
-195.924
-36.657
-195.924
-36.657
-36.657
HOST Buffer Current Control
TARGET
(MHz)
100.0000
133.3333
50.0000
66.6667
66.6667
33.3333
The current supplied at the HOST outputs is controlled by
two parameters:
1) the value of the programming resistor from the IREF
pin to ground (VSS), and
2) the multiplier factor determined by the logic setting of
the ISEL_0 and ISEL_1 pins.
3.1
Current Reference
48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB
standards.
Spread spectrum is disabled
Table 5: APICON Control
APICON
PIN 47
0
1
FREQUENCY SELECT CONTROL / APIC CLOCKS
PIN 21
SEL_A Input
(LVTTL)
APIC_0 Output /
SEL_A Latched
Input
PIN 22
SEL_B Input
(LVTTL)
APIC_1 Output /
SEL_B Latched
Input
PIN 23
SS_EN# Input
(LVTTL)
APIC_2 Output /
SS_EN# Latched
Input
The HOST output current is a mirrored and scaled copy
of the reference current flowing through the programming
resistor on the IREF pin. Conceptually, the circuit given in
Figure 2 shows how the mirror current is generated.
The voltage that appears at the IREF pin is one-third of
the voltage at the VDD_I pin. The reference current is
I
REF
1
×
VDD_I
3
.
=
R
IREF
3.2
Current Scaling
The mirrored reference current can be increased by
adding one or more copies of the mirror current together.
The additional current is controlled by the logic settings
on the ISEL_0 and ISEL_1 pins.
ISO9001
9.18.00
3
FS6158-01
Two-Way/Four Way Motherboard Clock Generator/Buffer IC
AMERICAN MICROSYSTEMS, INC.
September 2000
Table 6: Current Multiplier
ISEL_0
0
0
1
1
ISEL_1
0
1
0
1
MULTPLIER
I
O
= 5
×
I
REF
I
O
= 6
×
I
REF
I
O
= 4
×
I
REF
I
O
= 7
×
I
REF
Table 8: HOST Buffer Clock Outputs
Output
Voltage (V)
3.30
3.14
2.97
2.81
2.64
2.48
HIGH DRIVE CURRENT (mA)
AT PRIMARY SYSTEM CONFIGURATION
MIN.
0.00
-3.03
-5.66
-7.87
-9.67
-11.05
-11.98
-12.52
-12.77
-12.91
-12.99
-13.04
-13.07
-13.08
-13.09
-13.11
-13.12
-13.13
-13.13
-13.14
-13.15
TYP.
0.00
-4.22
-7.68
-10.30
-11.91
-12.56
-12.85
-13.07
-13.26
-13.42
-13.54
-13.64
-13.70
-13.73
-13.75
-13.76
-13.78
-13.79
-13.80
-13.81
-13.82
MAX.
0.00
-5.76
-9.86
-11.85
-12.45
-12.84
-13.16
-13.45
-13.72
-13.96
-14.17
-14.36
-14.52
-14.64
-14.71
-14.74
-14.76
-14.78
-14.80
-14.82
-14.83
Figure 2: Current Reference Circuit
VDD_I (3.3V)
2R
1.1V
Additional
Mirror
Current
Mirror
Current
ISEL_0:1
2.31
2.14
1.98
1.81
1.65
1.48
R
IREF
Reference
Current I
REF
R
IREF
HOST_N
R
S
R
P
HOST_P
R
S
R
P
1.32
1.15
0.99
0.82
0.66
0.49
Table 7: HOST Current Selection
PROGRAM
RESISTOR
R
IREF
475Ω (1%)
475Ω (1%)
475Ω (1%)
475Ω (1%)
221Ω (1%)
221Ω (1%)
221Ω (1%)
221Ω (1%)
REFERENCE
CURRENT
CURRENT
MULTIPLIER
I
REF
2.32mA
2.32mA
2.32mA
2.32mA
5mA
5mA
5mA
5mA
I
O
= 5
×
I
REF
I
O
= 6
×
I
REF
I
O
= 4
×
I
REF
I
O
= 7
×
I
REF
I
O
= 5
×
I
REF
I
O
= 6
×
I
REF
I
O
= 4
×
I
REF
I
O
= 7
×
I
REF
TRACE
IMPEDANCE
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
30Ω
25Ω
30Ω
25Ω
30Ω
25Ω
30Ω
25Ω
OUTPUT
VOLTAGE
0.71V
0.59V
0.85V
0.71V
0.56V
0.47V
0.99V
0.82V
0.75V
0.62V
0.90V
0.75V
0.60V
0.50V
1.05V
0.84V
0.33
0.16
0.00
Output Voltage (V)
0
0
-2
1
2
3
Output Current (mA)
-4
-6
-8
-10
-12
-14
-16
-18
-20
30Ω
50Ω
90Ω
Max VOH
NOTE: Shaded row indicates the Primary System Configuration
Data in this table represents nominal characterization data only
ISO9001
9.18.00
4
FS6158
-01
AMERICAN MICROSYSTEMS, INC.
Two-Way/Four Way Motherboard Clock Generator/Buffer IC
September 2000
4.0
Power Management
Table 9: Latency Table
SIGNAL
SIGNAL
STATE
Power
OFF
Power
ON
Output:
Device:
LATENCY
MIN.
2 clocks
2× 14REF
clocks
3ms
MAX.
3 clocks
3× 14REF
clocks
The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that places the device in a low power inac-
tive state without removing power from the device. All
internal clocks are turned off, and all clock outputs are
held low.
Since PWR_DWN# is asynchronous, the signal is syn-
chronized internally to each individual clock. As shown in
Figure 3, a falling-rising-falling edge sequence on any
individual clock output is required before that clock output
is disabled low. This edge sequence ensures that one
complete clock cycle will occur before the clock stops.
PWR_
DWN#
0
1
Upon the release of PWR_DWN# (power-up), external
circuitry should allow a minimum of 3ms for the PLL to
lock before enabling any clocks.
Figure 3: PWR_DWN# Timing
Any Clock
(internal)
PWR_DWN#
Any Clock
(output)
After 14REF
output shuts off...
VCO
Crystal
Oscillator
Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.
3ms until clock is valid
5.0
Dual Function I/O Pins
Figure 4: I/O Pin Programming
Termination
Resistor
Device Solder
Pads
Several pins on this device serve as dual function in-
put/output pins. During the initial application of VDD to
the device, this type of pin functions as an input pin.
Upon completion of power-up, the logic state present on
the pin is latched internally, and the pin is converted to an
output driver.
An external 10kΩ pull-down resistor to ground is required
for a logic low and a 10kΩ pull-up resistor to the clock
output VDD is required for a logic high. The 10kΩ resistor
presents an insignificant load to the output driver that
should not affect the output clock.
Note that the latching of the logic state occurs only on the
application of the chip supply voltage (VDD). The logic
state on the pin is not latched if the PWR_DWN# signal is
used to power-down the device with VDD still applied.
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