Three high-resolution, low-jitter PLLs optimized for
frequency synthesis
Additional multiplier PLL for generation of high-
frequency VCXO function from inexpensive
fundamental mode crystals
Six CMOS clock outputs
Integrated VCXO circuitry for fine-tuning (typically +/-
100ppm) output frequencies
S0 and S1 control inputs can modify device power-up
function (see text)
Package: 16-pin (0.150”) SOIC
Custom default frequency patterns, pinouts, and
packages are available. Contact your local AMI Sales
Representative for more information.
The FS6477 is a CMOS clock generator IC designed to
minimize cost and component count in a variety of elec-
tronic systems. It is especially well suited to digital
video/audio systems such as digital set-top boxes.
Figure 1: Pin Configuration
SDA
VDD
VSS
XIN
XOUT
XTUNE
CLK_F/S1
CLK_E/S0
1
2
3
16
15
14
•
•
•
•
•
SCL
CLK_A
VDD
CLK_B
CLK_C
VSS
CLK_D
MODE
FS6477
4
5
6
7
8
13
12
11
10
9
Figure 2: Block Diagram
XIN
XOUT
XTUNE
VCXO +
Multiplier
PLL A
CLK_A
CLK_B
Divider
Array
PLL B
CLK_C
CLK_D
CLK_E/S0
PLL C
SCL
SDA
I
2
C-bus
Interface
Device
Control
CLK_F/S1
MODE
FS6477
Intel and Pentium are registered trademarks of Intel Corporation. Non-linear spread spectrum modulation profile is licensed under US Patent No. 5488627, Lexmark International, Inc. This document
contains information on a new product. Specifications and information herein are subject to change without notice.
ISO9001
4.28.00
IntSol2M
FS6477-01
Three-PLL VCXO Programmable Clock Generator IC
Advance Information
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
AMERICAN MICROSYSTEMS, INC.
April 2000
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TYPE
DI
U
O
P
P
AI
AO
AI
DI O
DI O
DI
U
U
U
NAME
SDA
VDD
VSS
XIN
XOUT
XTUNE
CLK_F/S1
CLK_E/S0
MODE
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
SCL
Serial interface data input/output
Power supply (3.3V nominal)
Ground
DESCRIPTION
Voltage-controlled crystal oscillator feedback
Voltage-controlled crystal oscillator drive
VCXO control voltage input
“F” clock output / S1 control input
“E” clock output / S0 control input
Device MODE select (see text)
“D” clock output
Ground
“C” clock output
“B” clock output
Power supply (5V to 3.3V)
“A” clock output
Serial interface clock input
DO
P
DO
DO
P
DO
DI
U
3.0
3.1
Functional Block Description
Voltage-Controlled Crystal
Oscillator (VCXO)
Figure 2: Typical VCXO Characteristic
VCXO Deviation vs. XTUNE Input (typical)
250
200
150
Deviation - ppm
100
50
0
0
-50
-100
-150
-200
V(XTUNE) - volts
0.5
1
1.5
2
2.5
3
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6477 system components.
Load capacitors are internal to the FS6477. No external
components (other than the crystal itself) are required for
operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin.
The oscillator operates the crystal resonator in the paral-
lel-resonant mode. “Pulling” of the crystal oscillation fre-
quency is accomplished by altering the effective load ca-
pacitance presented to the crystal. The actual amount
that changing the load capacitance alters the oscillator
frequency will depend on the characteristics of the crystal
as well as the oscillator circuit itself.
Specifically, the motional capacitance of the crystal (usu-
ally referred to by crystal manufacturers as C
1
), the static
capacitance of the crystal (C
0
), and the load capacitance
(C
L
) of the oscillator determine the “pulling” capability of
the crystal in the oscillator circuit.
ISO9001
4.28.00
2
FS6477-01
AMERICAN MICROSYSTEMS, INC.
Three-PLL VCXO Programmable Clock Generator IC
Advance Information
The PFD compares the two frequencies at its input and
will drive the VCO to run faster (or slower) until both fre-
quencies are equal. When this condition has been met:
April 2000
A simple formula to obtain the peak-to-peak “pulling” ca-
pability of a crystal oscillator is:
6
C
1
×
(
C
L
2
−
C
L
1
)
×
10
∆
f
(
ppm
)
=
2
×
(
C
0
+
C
L
2
)
×
(
C
0
+
C
L
1
)
where C
L1
and C
L2
are the two extremes of the applied
load capacitance.
EXAMPLE: A crystal with the following parameters is
used. With C
1
= 0.02pF, C
0
= 6pF, C
L1
= 10pF, and C
L2
=
20pF, the tuning range (peak-to-peak) is
f
VCO
N
F
f
REF
=
N
R
.
.
which can be re-arranged:
0
.
025
×
(
20
−
10
)
×
106
∆
f
=
=
300
ppm
.
2
×
(
6
+
20
)
×
(
6
+
10
)
N
f
VCO
=
f
REF
F
N
R
3.2
Multiplier
A simple Phase-Locked Loop multiplies the output fre-
quency of the VCXO by eight for use by the programma-
ble PLLs and Post Dividers. See below for a description
of PLL operation.
3.3.1 Reference Divider
The Reference Divider is designed for low phase jitter.
The divider accepts the output of the reference oscillator
and provides a divided-down frequency to the PFD. The
Reference Divider is an 8-bit divider, and can be pro-
grammed for any modulus from 1 to 255 by programming
the equivalent binary value. A divide-by-256 can also be
achieved by programming the eight bits to 00h.
3.3.2 Feedback Divider
The Feedback Divider is based on a dual-modulus divider
(also called dual-modulus prescaler) technique. It per-
mits division by any integer value between 56 and 16383.
Selected values below 56 are also permitted (see Table).
3.3
Phase Locked Loops
As shown in Figure 3, each PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal Loop Filter, a Voltage-Controlled Os-
cillator (VCO), and a Feedback Divider.
This is a standard phase- and frequency-locked loop ar-
chitecture that multiplies a reference frequency to a de-
sired frequency by a ratio of integers. This frequency
multiplication is exact.
Table 2: Feedback Modulus Below 56
FBKDIV[2:0]
FBKDIV[13:3]
000
001
9
17
25
33
41
49
57
010
-
18
26
34
42
50
58
011
-
-
27
35
43
51
59
100
-
-
-
36
44
52
60
101
-
-
-
-
45
53
61
110
-
-
-
-
-
54
62
111
-
-
-
-
-
-
63
00000000001
8
16
24
32
40
48
56
Figure 3: PLL Diagram
LFTC
00000000010
00000000011
00000000100
00000000101
f
VCO
REFDIV[7:0]
CP
Loop
Filter
f
REF
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
UP
Charge
Pump
DOWN
FBKDIV[10:0]
Voltage
Controlled
Oscillator
00000000110
00000000111
FEEDBACK DIVIDER MODULUS
Feedback
Divider
(N
F
)
ISO9001
4.28.00
3
FS6477-01
Three-PLL VCXO Programmable Clock Generator IC
Advance Information
3.3.3 Post Divider
The Post Divider is actually constructed of a cascade of
three programmable dividers, as shown in Figure 4.
AMERICAN MICROSYSTEMS, INC.
April 2000
applications where frequencies must be achieved
exactly.
It changes the overall device frequency equation to:
N
f
CLK
=
f
REF
F
N
R
1
N
P
Figure 4: Post Divider
POSTCTL_x [3:0]
Note that a nominal 50/50 duty factor is always preserved
(even for selections which have an odd modulus).
Control ROM
3.4
f
IN
Post
Divider 1
Post
Divider 2
POST DIVIDER (N
P
)
Device Control Overview
Post
Divider 3
f
OUT
The modulus of the overall combination is controlled by
the appropriate register bits (see Table 7).
The Post Divider performs some useful functions. First, it
allows the VCO to be operated in a narrower range of
speeds compared to the output frequencies that are
needed in many applications.
Second, the extra integer in the denominator permits
more flexibility in the programming of the loop for many
The FS6477 contains an internal ROM that holds four
different device configurations. When the MODE pin is
LOW, the bi-directional pins (CLK_E/S0 and CLK_F/S1)
are made to be INPUTS and the voltage levels applied to
those pins select which one of those four states is made
active.
When the MODE pin is taken HIGH, the levels on those
pins are latched, and both bi-directional pins are made to
be OUTPUTS.
Any desired new configuration can be loaded into the
registers via the I2C interface at any time. The configura-
tion will not become applied to the PLLs or Post Dividers
until the appropriate SWAP bits have been set to a “1”.
Table 3: Programmable Register Map
Note: All programmable registers are cleared (set to “0”) on power-up.
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