FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
1.0 Features
• Three on-chip PLLs with programmable reference
and feedback dividers
• Four independently programmable muxes and post
dividers
• I
2
C™-bus serial interface
• Programmable power-down of all PLLs and output
clock drivers
Data Sheet
• One PLL and two mux/post-divider combinations can
be modified by SEL_CD input
• Tristate outputs for board testing
• 5V to 3.3V operation
• Accepts 5MHz to 27MHz crystal resonators
• Commercial (FS6377-01) and industrial (FS6377-01i)
temperature ranges
2.0 Description
The FS6377 is a CMOS clock generator IC designed to
minimize cost and component count in a variety of
electronic systems. Three I
2
C-programmable phase-
locked loops feeding four programmable muxes and post
dividers provide a high degree of flexibility.
SDA
SEL_CD
PD
VSS
XIN
XOUT
OE
VDD
1
2
3
16
15
14
SCL
CLK_A
VDD
CLK_B
CLK_C
VSS
CLK_D
ADDR
FS6377
4
5
6
7
8
13
12
11
10
9
16-pin (0.150") SOIC
Figure 1: Pin Configuration
XIN
XOUT
Reference
Oscillator
PLL A
Mux A
Post
Divider A
CLK_A
PD
Power Down
Control
PLL B
Mux B
Post
Divider B
CLK_B
SCL
SDA
ADDR
I
2
C-bus
Interface
PLL C
Mux C
Post
Divider C
CLK_C
SEL_CD
Mux D
Post
Divider D
CLK_D
OE
FS6377
Figure 2: Block Diagram
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Table 1. Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
DI
u
O
DI
P
AI
AO
DI
u
P
DI
P
DO
DO
P
DO
DI
u
u
u
Data Sheet
Name
SDA
SEL_CD
PD
VSS
XIN
XOUT
OE
VDD
ADDR
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
SCL
Description
Serial interface data input/output
Selects one of two PLL C, mux D/C and post divider C/D combinations
Power-down input
Ground
Crystal oscillator input
Crystal oscillator output
Output enable input
Power supply (5V to 3.3V)
Address select
D clock output
Ground
C clock output
B clock output
Power supply (5V to 3.3V)
A clock output
Serial interface clock input
U
DI
u
DO
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input With Internal Pull-Up; DI
D
= Input With Internal Pull-Down; DIO = Digital Input/Output;
DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
3.0 Functional Block Description
3.1 Phase Locked Loops
Each of the three on-chip phase-locked loops (PLLs) is a
standard phase- and frequency-locked loop architecture
that multiplies a reference frequency to a desired
frequency by a ratio of integers. This frequency
multiplication is exact.
As shown in Figure 3, each PLL consists of a reference
divider, a phase-frequency detector (PFD), a charge
pump, an internal loop filter, a voltage-controlled oscillator
(VCO), and a feedback divider.
During operation, the reference frequency (f
REF
), generated
by the on-board crystal oscillator, is first reduced by the
reference divider. The divider value is called the
"modulus," and is denoted as N
R
for the reference divider.
The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (f
VCO
) through
the charge pump and loop filter. The VCO provides a high-
speed, low noise, continuously variable frequency clock
source for the PLL. The output of the VCO is fed back to
the PFD through the feedback divider (the modulus is
denoted by N
F
) to close the loop.
REFDIV[7:0]
CP
LFTC
Loop
Filter
f
REF
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
f
PD
UP
Charge
Pump
DOWN
FBKDIV[10:0]
Voltage
Controlled
Oscillator
f
VCO
Feedback
Divider
(N
F
)
Figure 3: PLL Diagram
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frquency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference
frequency and the VCO frequency is:
f
VCO
=
f
REF
( )
N
F
N
R
.
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
3.1.1 Reference Divider
The reference divider is designed for low phase jitter. The
divider accepts the output of the reference oscillator and
provides a divided-down frequency to the PFD. The
reference divider is an 8-bit divider, and can be
Data Sheet
programmed for any modulus from 1 to 255 by
programming the equivalent binary value. A divide-by-256
can also be achieved by programming the eight bits to
00h.
3.1.2 Feedback Divider
The feedback divider is based on a dual-modulus pre-
scaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the
programmable feedback divider because of the high
speeds at which the VCO can operate. The dual-modulus
technique insures reliable operation at any speed that the
VCO can achieve and reduces the overall power
consumption of the divider.
For example, a fixed divide-by-eight could be used in the
feedback divider. Unfortunately, a divide-by-eight would
limit the effective modulus of the entire feedback divider to
multiples of eight. This limitation would restrict the ability of
the PLL to achieve a desired input-frequency-to-output-
frequency ratio without making both the reference and
feedback divider values comparatively large.
A large feedback modulus means that the divided VCO
frequency is relatively low, requiring a wide loop band-
width to permit the low frequencies. A narrow loop band-
width tuned to high frequencies is essential to minimizing
jitter; therefore, divider moduli should always be as small
as possible.
To understand the operation, refer to Figure 4. The M-
counter (with a modulus always equal to M) is cascaded
with the dual-modulus prescaler. The A-counter controls
the modulus of the prescaler. If the value programmed into
the A-counter is A, the prescaler will be set to divide by
N+1 for A prescaler outputs. Thereafter, the prescaler
divides by N until the M-counter output resets the A-
counter, and the cycle begins again. Note that N=8 and A
and M are binary numbers.
Suppose that the A-counter is programmed to zero. The
modulus of the prescaler will always be fixed at N; and the
entire modulus of the feedback divider becomes MxN.
Next, suppose that the A-counter is programmed to a one.
This causes the prescaler to switch to a divide-by-N+1 for
its first divide cycle and then revert to a divide-by-N. In
effect, the A-counter absorbs (or "swallows") one extra
clock during the entire cycle of the feedback divider. The
overall modulus is now seen to be equal to MxN+1.
This example can be extended to show that the feedback
divider modulus is equal to MxN+A, where A<M.
f
VCO
Dual
Modulus
Prescaler
FBKDIV[2:0]
M
Counter
f
PD
FBKDIV[10:3]
A
Counter
Figure 4: Feedback Divider
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
3.1.3 Feedback Divider Programming
For proper operation of the feedback divider, the A-counter
must be programmed only for values that are less than or
equal to the M-counter. Therefore, not all divider moduli
below 56 are available for use. The selection of divider
values is listed in Table 2.
Data Sheet
Above a modulus of 56, the feedback divider can be
programmed to any value up to 2047.
Table 2. Feedback Divider Modulus Under 56
M-Counter:
FBKDIV[10:3]
000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
8
16
24
32
40
48
56
001
9
17
25
33
41
49
57
18
26
34
42
50
58
27
35
43
51
59
36
44
52
60
45
53
61
54
62
63
A-Counter: FBKDIV[2:0]
010
011
100
101
110
111
Feedback Divider Modulus
3.2 Post Divider Muxes
As shown in Figure 2, an input mux in front of each post
divider stage can select from any one of the PLL
frequencies or the reference frequency. The frequency se-
lection is done via the I
2
C-bus.
The input frequency on two of the four muxes (mux C and
D in Figure 2) can be changed without reprogramming by
a logic-level input on the SEL_CD pin.
3.3 Post Dividers
The post divider performs several useful functions. First, it
allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it changes
the basic PLL equation to
divider moduli respectively, and f
CLK
and f
REF
are the output
and reference oscillator frequencies. The extra integer in
the denominator permits more flexibility in the
programming of the loop for many applications where
frequencies must be achieved exactly.
The modulus on two of the four post dividers muxes (post
dividers C and D in Figure 2) can be altered without
reprogramming by a logic level on the SEL_CD pin.
f
CLK
=
f
REF
( )( )
N
F
N
R
1
N
P
where N
F
, N
R
and N
P
are the feedback, reference and post
4.0 Device Operation
The FS6377 powers up with all internal registers cleared to
zero, delivering the crystal frequency to all outputs. For
operation to occur, the registers must be loaded in a most-
significant-bit (MSB) to least-significant-bit (LSB) order.
The register mapping of the FS6377 is shown in Table 3,
and I
2
C-bus programming information is detailed in Section
5.0.
Control of the reference, feedback and post dividers is
detailed in Table 5. Selection of these dividers directly
controls how fast the VCO will run. The maximum VCO
speed is noted in Table 13.
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
4.1 SEL_CD Input
The SEL_CD pin provides a way to alter the operation of
PLL C, muxes C and D and post dividers C and D without
having to reprogram the device. A logic-low on the
SEL_CD pin selects the control bits with a "C1" or "D1"
notation, per Table 3. A logic-high on the SEL_CD pin
selects the control bits with "C2" or "D2" notation, per
Data Sheet
Table 3.
Note that changing between two running frequencies us-
ing the SEL_CD pin may produce glitches in the output,
especially if the post-divider(s) is/are altered.
4.2 Power-Down and Output Enable
A logic-high on the PD pin powers down only those
portions of the FS6377 which have their respective
powerdown control bits enabled. Note that the PD pin has
an internal pull-up.
When a post divider is powered down, the associated
output driver is forced low. When all PLLs and post
4.3 Oscillator Overdrive
For applications where an external reference clock is
provided (and the crystal oscillator is not required), the
reference clock should be connected to XOUT and XIN
should be left unconnected (float).
For best results, make sure the reference clock signal is
as jitter-free as possible, can drive a 40pF load with fast
dividers are powered down the crystal oscillator is also
powered down. The XIN pin is forced low, and the XOUT
pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note
that this pin has an internal pull-up.
rise and fall times and can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the refer-
ence must be AC coupled to XOUT through a 0.01mF or
0.1mF capacitor. A minimum 1V peak-to-peak signal is
required to drive the internal differential oscillator buffer.
5.0 I
2
C-bus Control Interface
This device is a read/write slave device
meeting all Philips I
2
C-bus specifications
except a "general call." The bus has to be
controlled by a master device that generates
the serial clock SCL, controls bus access and
generates the START and STOP conditions while the
device works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master device
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus
is not busy. During the data transfer, the data line (SDA)
must remain stable whenever the clock line (SCL) is high.
Changes in the data line while the clock line is high will be
determines which mode is activated. A device that sends
data onto the bus is defined as the transmitter, and a
device receiving data as the receiver.
I
2
C-bus logic levels noted herein are based on a
percentage of the power supply (V
DD
). A logic-one
corresponds to a nominal voltage of V
DD
, while a logic-zero
corresponds to ground (V
SS
).
interpreted by the device as a START or STOP condition.
The following bus conditions are defined by the I
2
C-bus
protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
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