ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 3; 4
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.375V ~ 2.625V, V
DDQ
= 2.375V ~ 2.625V
Auto & Self refresh
32ms refresh period (4K cycle)
SSTL-2 I/O interface
100pin LQFP package
M13S32321A
256K x 32 Bit x 4 Banks
Double Data Rate SDRAM
Ordering Information :
PRODUCT NO.
M13S32321A -5L
MAX FREQ
200MHz
VDD
2.5V
PACKAGE
100 LQFP
COMMENTS
Pb-free
M13S32321A -6L
166MHz
2.5V
100 LQFP
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
1/50
ESMT
Functional Block Diagram
CLK
CLK
CKE
Address
Mode Register &
Extended Mode
Register
M13S32321A
Clock
Generator
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DM
Column Decoder
DQ
CLK, CLK
DLL
DQS
DQS
Pin Arrangement
DQ29
V
SSQ
DQ30
DQ31
V
SS
V
DDQ
N.C
N.C
N.C
N.C
N.C
V
SSQ
N.C
DQS
V
DDQ
V
DD
DQ0
DQ1
V
SSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A
7
A
6
A
5
A
4
V
SS
A
9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
DD
A
3
A
2
A
1
A
0
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
2/50
ESMT
Pin Description
(M13S32321A)
Pin Name
Function
Address inputs
- Row address A0~A9
- Column address A0~A7
A8/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi- directional Data Strolle.
Pin Name
M13S32321A
Function
A0~A9,
BA0,BA1
DM0~3
DQ Mask enable in write cycle.
DQ0~DQ31
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
NC
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL-2
No connection
V
SS
V
DD
DQS
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
3/50
ESMT
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note :
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
1.0
50
M13S32321A
Unit
V
V
V
°C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= 0 to 70 °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
Output Low Current (Normal strength driver)
(V
OUT
= 0.373V)
Output High Current (Weak strength driver)
(V
OUT
=V
DDQ
-0.763V, min V
REF
, min V
TT
)
Output Low Current (Weak strength driver)
(V
OUT
= 0.763V)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
I
I
I
OZ
I
OH
I
OL
I
OH
I
OL
Min
2.375
2.375
0.49*V
DDQ
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
-2
-5
-16.8
+16.8
-9
+9
Max
2.625
2.625
0.51*V
DDQ
V
REF
+ 0.04
V
DDQ
+ 0.3
V
REF
- 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
2
5
Unit
V
V
V
V
V
V
V
V
1
2
Note
μ
A
μ
A
mA
mA
mA
mA
3
Notes 1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2.
3.
V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set equal
to V
REF
, and must track variations in the DC level of V
REF
.
V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
4/50
ESMT
DC Specifications
Parameter
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down Standby
Current
Idle Standby Current
Active
Current
Power-down
Standby
Symbol
Test Condition
-5
IDD0
IDD1
IDD2P
IDD2N
IDD3P
t
RC
= t
RC
(min) t
CK
= t
CK
(min)
Active – Precharge
Burst Length = 2 t
RC
= t
RC
(min), CL= 3
I
OUT
= 0mA, Active-Read- Precharge
CKE
≤
V
IL
(max), t
CK
= t
CK
(min), All
banks idle
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
=
t
CK
(min)
All banks ACT, CKE
≤
V
IL
(max), t
CK
=
t
CK
(min)
One bank; Active-Precharge, t
RC
=
t
RAS
(max),
t
CK
= t
CK
(min)
Burst Length = 2, CL= 3 , t
CK
= t
CK
(min), I
OUT
= 0mA
Burst Length = 2, CL= 3 , t
CK
= t
CK
(min)
t
RC
≥
t
RFC
(min)
CKE
≤
0.2V
120
175
20
70
20
M13S32321A
Version
-6
100
150
20
60
20
mA
mA
mA
mA
mA
Unit Note
Active Standby Current
IDD3N
90
80
mA
Operation Current (Read)
Operation Current (Write)
Auto Refresh Current
Self Refresh Current
IDD4R
IDD4W
IDD5
IDD6
260
210
190
3
220
180
160
3
mA
mA
mA
mA
1
Note 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Symbol
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.45
V
REF
- 0.45
V
DDQ
+0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V
DD
= 2.375V~2.625V, V
DDQ
=2.375V~2.625V, T
A
= 25 °C , f = 1MHz)
Parameter
Input capacitance
(A0~A9, BA0~BA1, CKE, CS , RAS , CAS ,
WE
)
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
Symbol
C
IN1
C
IN2
C
OUT
C
IN3
Min
2
2
4.0
4.0
Max
3
3
5
5
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
5/50
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
