SEMICONDUCTOR
TECHNICAL DATA
General Description
This planar stripe MOSFET has better characteristics, such as fast
switching time, low on resistance, low gate charge and excellent
avalanche characteristics. It is mainly suitable for electronic ballast and
switching mode power supplies.
FEATURES
・V
DSS(Min.)
= 500V, I
D
= 5.5A
・R
DS(ON)
=1.0
Ω(Max)
@V
GS
=10V
・Qg(typ.)
=16nC
1
2
3
KF7N50D/I
N CHANNEL MOS FIELD
EFFECT TRANSISTOR
KF7N50D
A
C
K
D
L
B
H
G
F
F
J
E
N
M
DIM MILLIMETERS
_
A
6.60 + 0.20
_
6.10 + 0.20
B
_
5.34 + 0.30
C
_
D
0.70 + 0.20
_
E
2.70 + 0.15
_
2.30 + 0.10
F
0.96 MAX
G
0.90 MAX
H
_
1.80 + 0.20
J
_
2.30 + 0.10
K
_
0.50 + 0.10
L
_
M
0.50 + 0.10
0.70 MIN
N
0.1 MAX
O
1. GATE
2. DRAIN
3. SOURCE
MAXIMUM RATING
(Tc=25℃)
CHARACTERISTIC
Drain-Source Voltage
Gate-Source Voltage
@T
C
=25℃
Drain Current
@T
C
=100℃
Pulsed (Note1)
Single Pulsed Avalanche Energy
(Note 2)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Drain Power
Dissipation
Tc=25℃
P
D
Derate above25℃
T
j
T
stg
0.56
150
-55½150
W/℃
℃
℃
1
O
SYMBOL
V
DSS
V
GSS
I
D
RATING
KF7N50D/I
500
±30
5.5
3.5
UNIT
V
V
A
DPAK (1)
KF7N50I
H
J
I
DP
E
AS
E
AR
dv/dt
21
B
DIM
A
B
D
A
C
MILLIMETERS
180
4
4.5
69.4
mJ
K
M
_
6.6
+
0.2
_
6.1
+
0.2
_
5.34
+
0.3
_
0.7
+
0.2
_
9.3
+
0.3
_
2.3
+
0.2
_
0.76
+
0.1
_
2.3
+
0.1
_
0.5
+
0.1
_
1.8
+
0.2
_
0.5
+
0.1
_
1.0
+
0.1
0.96 MAX
_
1.02
+
0.3
mJ
V/ns
P
N
C
D
E
F
G
G
E
H
W
F
F
L
J
K
L
M
Maximum Junction Temperature
Storage Temperature Range
Thermal Characteristics
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-
Ambient
2
3
1. GATE
2. DRAIN
3. SOURCE
N
P
R
thJC
R
thJA
1.8
110
℃/W
IPAK(1)
℃/W
* : Drain current limited by maximum junction temperature.
PIN CONNECTION
D
G
S
2011. 10 . 4
Revision No : 0
1/6
KF7N50D/I
ELECTRICAL CHARACTERISTICS
(Tc=25℃)
CHARACTERISTIC
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature Coefficient
Drain Cut-off Current
Gate Threshold Voltage
Gate Leakage Current
Drain-Source ON Resistance
BV
DSS
ΔBV
DSS
/ΔT
j
I
DSS
V
th
I
GSS
R
DS(ON)
I
D
=250μ V
GS
=0V
A,
I
D
=250μ Referenced to 25℃
A,
V
DS
=500V, V
GS
=0V,
V
DS
=V
GS
, I
D
=250μ
A
V
GS
=±30V, V
DS
=0V
V
GS
=10V, I
D
=2.7A
500
-
-
2.5
-
-
-
0.5
-
-
-
0.83
-
-
10
4.5
±100
1.0
V
V/℃
μ
A
V
nA
Ω
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-on Delay time
Turn-on Rise time
Turn-off Delay time
Turn-off Fall time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Source-Drain Diode Ratings
Continuous Source Current
Pulsed Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
I
S
V
GS
<V
th
I
SP
V
SD
t
rr
Q
rr
I
S
=5.5A, V
GS
=0V
I
S
=7A, V
GS
=0V,
s
dIs/dt=100A/μ
-
-
-
-
-
-
310
2.7
28
1.4
-
-
V
ns
μ
C
-
-
7
A
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
V
DS
=25V, V
GS
=0V, f=1.0MHz
V
DD
=200V, I
D
=7A
R
G
=25Ω
V
GS
=10V
(Note4,5)
-
-
-
-
-
50
25
710
95
8.5
-
-
-
-
-
pF
V
DS
=400V, I
D
=7A
V
GS
=10V
(Note4,5)
-
-
-
-
-
16
3.5
6.0
20
25
-
-
-
-
-
ns
nC
Note 1) Repetivity rating : Pulse width limited by junction temperature.
Note 2) L = 7.0mH, I
S
=7A, V
DD
=50V, R
G
= 25Ω, Starting T
j
= 25℃.
Note 3) I
S
≤7A,
dI/dt≤100A/㎲, V
DD
≤BV
DSS
, Starting T
j
= 25℃.
Note 4) Pulse Test : Pulse width
≤
300㎲, Duty Cycle
≤
2%.
Note 5) Essentially independent of operating temperature.
Marking
1
1
KF7N50
001
D
2
KF7N50
001
I
2
1
PRODUCT NAME
2
LOT NO
2011. 10 . 4
Revision No : 0
2/6
KF7N50D/I
Fig1. I
D
- V
DS
10
2
Fig2. I
D
- V
GS
V
DS
=30V
Drain Current I
D
(A)
Drain Current I
D
(A)
V
GS
=10V
10
1
10
1
V
GS
=7V
100
C
10
0
V
GS
=5V
10
0
25
C
10
-1
10
0.1
1
10
100
-1
2
4
6
8
10
Drain - Source Voltage V
DS
(V)
Gate - Source Voltage V
GS
(V)
Fig3. BV
DSS
- Tj
Normalized Breakdown Voltage BV
DSS
1.2
3.0
V
GS
= 0V
I
DS
= 250
Fig4. R
DS(ON)
- I
D
On - Resistance R
DS(ON)
(Ω)
2.5
2.0
1.5
1.0
0.5
0.2
0
V
GS
=7V
1.1
1.0
V
GS
=10V
0.9
0.8
-100
-50
0
50
100
150
3
6
9
12
15
18
Junction Temperature Tj ( C )
Drain Current I
D
(A)
Fig5. I
S
- V
SD
10
2
Fig6. R
DS(ON)
- Tj
3.0
V
GS
=10V
I
D
= 3.5A
Reverse Drain Current I
S
(A)
Normalized On Resistance
2.5
2.0
1.5
1.0
0.5
10
1
100
C
25
C
10
0
10
-1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.0
-100
-50
0
50
100
150
Source - Drain Voltage V
SD
(V)
Junction Temperature Tj ( C)
2011. 10 . 4
Revision No : 0
3/6
KF7N50D/I
Fig 7. C - V
DS
10
4
12
I
D
=7 A
Fig8. Qg- V
GS
Gate - Source Voltage V
GS
(V)
10
8
6
4
2
0
0
3
6
9
12
15
18
21
24
V
DS
= 400V
Capacitance (pF)
10
3
Ciss
10
2
Coss
10
1
Crss
10
0
0
5
10
15
20
25
30
35
40
Drain - Source Voltage V
DS
(V)
Gate - Charge Qg (nC)
Fig9. Safe Operation Area
10
2
Operation in this
area is limited by R
DS(ON)
Fig10. I
D
- T
j
6
10µs
5
10
1
100µs
1ms
Drain Current I
D
(A)
Drain Current ID (A)
4
3
2
1
0
10
0
10ms
DC
10
-1
Tc= 25 C
Tj = 150 C
2
Single pulse
10
0
10
10
1
10
2
10
3
0
25
50
75
100
125
150
Drain - Source Voltage V
DS
(V)
Junction Temperature Tj (
C
)
Fig11. Transient Thermal Response Curve
10
1
Transient Thermal Resistance
10
0
Duty=0.5
0.2
P
DM
0.1
t
1
t
2
10
-1
0.05
0.02
0.01
g
Sin
le
lse
Pu
- Duty Factor, D= t
1
/t
2
T
j(max)
- T
c
- R
thJC
=
P
D
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-2
10
-5
TIME (sec)
2011. 10 . 4
Revision No : 0
4/6
KF7N50D/I
Fig12. Gate Charge
VGS
10 V
ID
Fast
Recovery
Diode
0.8 VDSS
1.0 mA
ID
Q
V
DS
VGS
Qgs
Qgd
Qg
Fig13. Single Pulsed Avalanche Energy
1
EAS=
LI
AS2
2
BV
DSS
BV
DSS
- V
DD
BV
DSS
L
I
AS
50V
25Ω
V
DS
10 V
VGS
I
D
(t)
V
DD
V
DS
(t)
Time
tp
Fig14. Resistive Load Switching
V
DS
90%
RL
0.5 VDSS
25
Ω
VDS
10V
VGS
V
GS
10%
t
d(off)
t
d(on)
t
on
tr
t
off
tf
2011. 10 . 4
Revision No : 0
5/6
微控制器 MCU
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