74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Rev. 02 — 19 January 2010
Product data sheet
1. General description
The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs
that enables bidirectional level translation. They feature one data input-output port (A and
B), a direction control input (DIR) and dual supply pins (V
CC(A)
and V
CC(B)
). Both V
CC(A)
and V
CC(B)
can be supplied at any voltage between 1.2 V and 5.5 V making the device
suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V,
3.3 V and 5.0 V). Pins A and DIR are referenced to V
CC(A)
and pin B is referenced to
V
CC(B)
. A HIGH on DIR allows transmission from A to B and a LOW on DIR allows
transmission from B to A.
The devices are fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data inputs at a valid
logic level.
2. Features
Wide supply voltage range:
V
CC(A)
: 1.2 V to 5.5 V
V
CC(B)
: 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114E Class 3A exceeds 4000 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
Suspend mode
NXP Semiconductors
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Latch-up performance exceeds 100 mA per JESD 78 Class II
±24
mA output drive (V
CC
= 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 16
μA
maximum I
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC1T45GW
74LVCH1T45GW
74LVC1T45GM
74LVCH1T45GM
74LVC1T45GF
74LVCH1T45GF
−40 °C
to +125
°C
XSON6
−40 °C
to +125
°C
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
×
1
×
0.5 mm
−40 °C
to +125
°C
Name
SC-88
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
4. Marking
Table 2.
Marking
Marking code
[1]
V5
X5
V5
X5
V5
X5
Type number
74LVC1T45GW
74LVCH1T45GW
74LVC1T45GM
74LVCH1T45GM
74LVC1T45GF
74LVCH1T45GF
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC_LVCH1T45_2
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 19 January 2010
2 of 30
NXP Semiconductors
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
5. Functional diagram
DIR
5
DIR
3
A
4
V
CC(A)
V
CC(B)
V
CC(A)
001aag885
A
B
B
V
CC(B)
001aag886
Fig 1. Logic symbol
Fig 2. Logic diagram
6. Pinning information
6.1 Pinning
74LVC1T45
74LVCH1T45
74LVC1T45
74LVCH1T45
V
CC(A)
GND
1
2
6
5
V
CC(B)
DIR
A
A
3
001aaj991
V
CC(A)
1
6
V
CC(B)
V
CC(A)
GND
74LVC1T45
74LVCH1T45
1
2
3
6
5
4
V
CC(B)
DIR
B
GND
2
5
DIR
3
4
B
A
4
B
001aaj992
001aaj993
Transparent top view
Transparent top view
Fig 3. Pin configuration SOT363
(SC-88)
Fig 4. Pin configuration SOT886
(XSON6)
Fig 5. Pin configuration SOT891
6.2 Pin description
Table 3.
Symbol
V
CC(A)
GND
A
B
DIR
V
CC(B)
Pin description
Pin
1
2
3
4
5
6
Description
supply voltage port A and DIR
ground (0 V)
data input or output
data input or output
direction control
supply voltage port B
74LVC_LVCH1T45_2
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 19 January 2010
3 of 30
NXP Semiconductors
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
7. Functional description
Table 4.
Function table
[1]
Input
DIR
L
H
X
Input/output
[2]
A
A=B
input
Z
B
input
B=A
Z
Supply voltage
V
CC(A)
, V
CC(B)
1.2 V to 5.5 V
1.2 V to 5.5 V
GND
[3]
[1]
[2]
[3]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The input circuit of the data I/O is always active.
When either V
CC(A)
or V
CC(B)
is at GND level, the device goes into suspend mode.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[4]
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+6.5
+6.5
-
+6.5
-
V
CCO
+ 0.5
+6.5
±50
100
-
+150
250
Unit
V
V
mA
V
mA
V
V
mA
mA
mA
°C
mW
V
I
< 0 V
[1]
−50
−0.5
−50
[1][2][3]
[1]
[2]
V
O
< 0 V
Active mode
Suspend or 3-state mode
V
O
= 0 V to V
CCO
I
CC(A)
or I
CC(B)
−0.5
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
[4]
-
The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
V
CCO
is the supply voltage associated with the output port.
V
CCO
+ 0.5 V should not exceed 6.5 V.
For SC-88 package: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 package: above 118
°C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC(A)
V
CC(B)
V
I
Recommended operating conditions
Parameter
supply voltage A
supply voltage B
input voltage
Conditions
Min
1.2
1.2
0
Max
5.5
5.5
5.5
Unit
V
V
V
74LVC_LVCH1T45_2
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 19 January 2010
4 of 30
NXP Semiconductors
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Table 6.
Symbol
V
O
T
amb
Δt/ΔV
Recommended operating conditions
…continued
Parameter
output voltage
ambient temperature
input transition rise and fall rate
V
CCI
= 1.2 V
V
CCI
= 1.4 V to 1.95 V
V
CCI
= 2.3 V to 2.7 V
V
CCI
= 3 V to 3.6 V
V
CCI
= 4.5 V to 5.5 V
[2]
Conditions
Active mode
Suspend or 3-state mode
[1]
Min
0
0
−40
-
-
-
-
-
Max
V
CCO
5.5
+125
20
20
20
10
5
Unit
V
V
°C
ns/V
ns/V
ns/V
ns/V
ns/V
[1]
[2]
V
CCO
is the supply voltage associated with the output port.
V
CCI
is the supply voltage associated with the input port.
10. Static characteristics
Table 7.
Typical static characteristics at T
amb
= 25
°C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
OH
V
OL
I
I
I
BHL
I
BHH
I
BHLO
I
BHHO
I
OZ
I
OFF
HIGH-level output voltage
LOW-level output voltage
input leakage current
bus hold LOW current
bus hold HIGH current
bus hold LOW overdrive
current
bus hold HIGH overdrive
current
OFF-state output current
power-off leakage current
Conditions
V
I
= V
IH
or V
IL
I
O
=
−3
mA; V
CCO
= 1.2 V
V
I
= V
IH
or V
IL
I
O
= 3 mA; V
CCO
= 1.2 V
DIR input; V
I
= 0 V to 5.5 V;
V
CCI
= 1.2 V to 5.5 V
A or B port; V
I
= 0.42 V; V
CCI
= 1.2 V
A or B port; V
I
= 0.78 V; V
CCI
= 1.2 V
A or B port; V
CCI
= 1.2 V
A or B port; V
CCI
= 1.2 V
A or B port; V
O
= 0 V or V
CCO
;
V
CCO
= 1.2 V to 5.5 V
A port; V
I
or V
O
= 0 V to 5.5 V;
V
CC(A)
= 0 V; V
CC(B)
= 1.2 V to 5.5 V
B port; V
I
or V
O
= 0 V to 5.5 V;
V
CC(B)
= 0 V; V
CC(A)
= 1.2 V to 5.5 V
C
I
C
I/O
input capacitance
input/output capacitance
DIR input; V
I
= 0 V or 3.3 V;
V
CC(A)
= V
CC(B)
= 3.3 V
A and B port; suspend mode;
V
O
= 3.3 V or 0 V; V
CC(A)
= V
CC(B)
= 3.3 V
[1]
[2]
[1]
Min
-
-
-
-
-
-
-
-
-
-
-
-
Typ
1.09
0.07
-
19
−19
19
−19
-
-
-
2.2
6.0
Max
-
-
±1
-
-
-
-
±1
±1
±1
-
-
Unit
V
V
μA
μA
μA
μA
μA
μA
μA
μA
pF
pF
[2]
[2]
[2][3]
[2][3]
[1]
[1]
[2]
[3]
V
CCO
is the supply voltage associated with the output port.
V
CCI
is the supply voltage associated with the data input port.
To guarantee the node switches, an external driver must source/sink at least I
BHLO
/ I
BHHO
when the input is in the range V
IL
to V
IH
.
74LVC_LVCH1T45_2
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 19 January 2010
5 of 30
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
