Custom frequency selections available - contact your
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•
•
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Figure 1: Pin Configuration
XIN
VDD
XTUNE
VSS
1
8
The FS6128 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6128 is circuitry that implements a
voltage-controlled crystal oscillator when an external
resonator (nominally 13.5MHz) is attached. The VCXO
allows device frequencies to be precisely adjusted for use
in systems that have frequency matching requirements,
such as digital satellite receivers.
A high-resolution phase-locked loop generates an output
clock (CLK) through a post-divider. The CLK frequency is
ratiometrically derived from the VCXO frequency. The
locking of the CLK frequency to other system reference
frequencies can eliminate unpredictable artifacts in video
systems and reduce electromagnetic interference (EMI)
due to frequency harmonic stacking.
XOUT
VSS
n/c
CLK
Table 1: Crystal / Output Frequencies
DEVICE
FS6128-01
f
XIN
(MHz)
13.5
CLK (MHz)
27
XTUNE Range
0-2 V
FS6128
2
3
4
7
6
5
NOTE: Contact AMI for custom PLL frequencies
8-pin (0.150″) SOIC
Figure 2: Block Diagram
XIN
VCXO
XOUT
XTUNE
PLL
DIVIDER
CLK
FS6128
ISO9001
2.27.02
FS6128-01
PLL Clock Generator IC with VCXO
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
1
2
3
4
5
6
7
8
TYPE
AI
P
AI
P
DO
-
DO
AO
NAME
XIN
VDD
XTUNE
VSS
CLK
n/c
VSS
XOUT
VCXO Feedback
Power Supply (+3.3V)
VCXO Tune
Ground
Clock Output
No Connection
Ground
VCXO Drive
DESCRIPTION
3.0
3.1
Functional Block Description
Phase-Locked Loop (PLL)
The on-chip PLL is a standard frequency- and phase-
locked loop architecture. The PLL multiplies the reference
oscillator to the desired frequency by a ratio of integers.
The frequency multiplication is exact with a zero synthe-
sis error.
3.2
Voltage-Controlled Crystal
Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6128 system components.
Loading capacitance for the crystal is internal to the
FS6128. No external components (other than the reso-
nator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin. The
value of this voltage controls the effective capacitance
presented by the VCXO to the crystal.
When using a crystal with a VCXO, it is important that the
crystal load capacitance (as specified in Table 4: Oper-
ating Conditions be matched to the load capacitance as
presented by the VCXO. The crystal must be specified
with the correct load capacitance to obtain the maximum
tuning range.
The oscillator operates the crystal resonator in the paral-
lel-resonant mode. Crystal warping, or the “pulling” of the
crystal oscillation frequency, is accomplished by altering
the effective load capacitance presented to the crystal by
the oscillator circuit. The actual amount that changing the
load capacitance alters the oscillator frequency will be
dependent on the characteristics of the crystal as well as
the oscillator circuit itself.
Specifically, the motional capacitance of the crystal (usu-
ally referred to by crystal manufacturers as C
1
), the static
capacitance of the crystal (C
0
), and the load capacitance
(C
L
) of the oscillator determine the warping capability of
the crystal in the oscillator circuit.
A simple formula to obtain the warping capability of a
crystal oscillator is:
6
C
1
×
(
C
L
2
−
C
L
1
)
×
10
∆
f
(
ppm
)
=
2
×
(
C
0
+
C
L
2
)
×
(
C
0
+
C
L
1
)
where C
L1
and C
L2
are the two extremes of the applied
load capacitance.
EXAMPLE: A crystal with the following parameters is
used. With C
1
= 0.02pF, C
0
= 5pF, C
L1
= 13pF, and C
L2
=35pF, the coarse tuning range is
0
.
02
×
(
35
−
13
)
×
106
∆
f
=
≈
305
ppm
.
2
×
(
5
+
35
)
×
(
5
+
13
)
ISO9001
2
2.27.02
FS6128-01
PLL Clock Generator IC with VCXO
4.0
Electrical Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
Supply Voltage (V
SS
= ground)
Input Voltage, dc
Output Voltage, dc
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Storage Temperature Range (non-condensing)
Ambient Temperature Range, Under Bias
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
V
DD
V
I
V
O
I
IK
I
OK
T
S
T
A
T
J
MIN.
V
SS
-0.5
V
SS
-0.5
V
SS
-0.5
-50
-50
-65
-55
MAX.
7
V
DD
+0.5
V
DD
+0.5
50
50
150
125
125
260
2
UNITS
V
V
V
mA
mA
°C
°C
°C
°C
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 4: Operating Conditions
PARAMETER
Supply Voltage
Ambient Operating Temperature Range
Crystal Resonator Frequency
Crystal Resonator Motional Capacitance
Crystal Loading Capacitance
SYMBOL
V
DD
T
A
f
XTAL
C
1(xtal)
C
L(xtal)
Fundamental Mode
AT cut
AT cut
CONDITIONS/DESCRIPTION
3.3V ± 10%
MIN.
3.0
0
5
13.5
25
20
TYP.
3.3
MAX.
3.6
70
18
UNITS
V
°C
MHz
fF
pF
ISO9001
3
2.27.02
FS6128-01
PLL Clock Generator IC with VCXO
Table 5: DC Electrical Specifications
Unless otherwise stated, V
DD
= 3.3V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
Overall
Supply Current, Dynamic, with Loaded
Outputs
Supply Current, Static
Voltage Controlled Crystal Oscillator
Crystal Loading Capacitance
Crystal Resonator Motional Capacitance
VCXO Tuning Range
VCXO Tuning Characteristic
Crystal Drive Level
Clock Output (CLK)
High-Level Output Source Current *
Low-Level Output Sink Current *
Output Impedance *
Short Circuit Source Current *
Short Circuit Sink Current *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
I
DD
I
DD
f
XTAL
= 13.5MHz; C
L
= 10pF, V
DD
= 3.6V
XIN = 0V, V
DD
= 3.6V
30
3
mA
mA
C
L(xtal)
C
1(xtal)
As seen by a crystal connected to XIN and
XOUT (@ V
XTUNE
= 1V)
AT cut
f
XTAL
= 13.5MHz; C
L(xtal)
= 20pF; C
1(xtal)
= 25fF
20
25
300
150
200
pF
fF
ppm
ppm/V
uW
Note: positive change of XTUNE =
positive change of VCXO frequency
R
XTAL
=20Ω; C
L
= 20pF
I
OH
I
OL
z
OH
z
OL
I
OSH
I
OSL
V
O
= 2.0V
V
O
= 0.4V
V
O
= 0.1V
DD
; output driving high
V
O
= 0.1V
DD
; output driving low
V
O
= 0V; shorted for 30s, max.
V
O
= 3.3V; shorted for 30s, max.
-40
17
25
25
-55
55
mA
mA
Ω
mA
mA
ISO9001
4
2.27.02
FS6128-01
PLL Clock Generator IC with VCXO
Table 6: AC Timing Specifications
Unless otherwise stated, V
DD
= 3.3V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ from typical.
PARAMETER
Overall
VCXO Stabilization Time *
PLL Stabilization Time *
Synthesis Error
Clock Output (CLK)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Long Term (σ
y
(τ)) *
Rise Time *
Fall Time *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
t
VCXOSTB
t
PLLSTB
From power valid
From VCXO stable
(unless otherwise noted in Frequency Table)
10
500
0
ms
us
ppm
Ratio of high pulse width (as measured from rising
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