and tristate banks of clock outputs independently of
the serial interface
Active-low PWR_DWN# signal allows shuts down the
PLL and disables outputs low
Supports Test Mode and tristate output control to fa-
cilitate board testing
Available in a 56-pin SSOP and TSSOP
66REF
CK66_0:4
CK66_5
VSS_66
VDD_P
SEL_Q
SEL_R
SEL_S
SCL
SDA
÷2
PCI_0:5
PCI_6:7
SMBus
Output
Control
PCI_8:11
VSS_P
VDD_48
CK48_0
PWR_DWN#
PLL
CK48_1
VSS_48
VDD_R
•
•
14REF
REF_0:1
•
•
•
FS6159
Figure 2: Pin Configuration
VSS_N 1
14REF 2
VDD_N 3
66REF 4
VSS_P 5
PCI_0 6
56 VDD_R
55 REF_1
54 REF_0
53 VSS_R
52 VDD_66
51 CK66_5
50 CK66_4
49 VSS_66
48 VSS_66
47 CK66_3
46 CK66_2
45 VDD_66
44 VDD_66
43 CK66_1
42 CK66_0
41 VSS_66
40 VDD
39 VSS
38 VDD_48
37 CK48_1
36 CK48_0
35 VSS_48
34 SEL_S
33 PWR_DWN#
32 VDD_S
31 VSS_S
30 SCL
29 SDA
VSS_R
Table 1: Clock Parameters
CLOCK
GROUP
CK66
PCI
REF
CK48
#
PINS
6
12
2
2
SUPPLY
VOLTAGE
3.3V
3.3V
3.3V
3.3V
SUPPLY
GROUP
VDD_66
VDD_P
VDD_R
VDD_48
FREQUENCY
(MHz)
66.67
33.33
14.318
48.008
SKEW
(MAX)
250ps
300ps
-
-
PCI_1 7
VDD_P 8
VSS_P 9
PCI_2 10
PCI_3 11
VDD_P 12
VSS_P 13
PCI_4 14
PCI_5 15
VDD_P 16
PCI_6 17
PCI_7 18
VSS_P 19
FS6159-01
Table 2: Clock Offsets
RELATION
CK66 leads PCI
PHASE
0°
MIN
1.5ns
TYP
MAX
3.5ns
VDD_P 20
PCI_8 21
PCI_9 22
VSS_P 23
PCI_10 24
PCI_11 25
VDD_P 26
SEL_Q 27
SEL_R 28
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
ISO9001
2.27.02
IntFF
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer IC
Table 3: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
2
4
36, 37
42, 43, 46,
47, 50, 51
6, 7, 10, 11, 14,
15, 17, 18,
21, 22, 24, 25
33
54, 55
30
29
27, 28, 34
40
38
44, 45, 52
3
8, 12, 16,
20, 26
56
32
39
35
41, 48, 49
1
5, 9, 13,
19, 23
53
31
TYPE
DI
DI
DO
DO
DO
NAME
14REF
66REF
CK48_0:1
CK66_0:5
PCI_0:11
DESCRIPTION
One 14.318MHz clock input, used to develop the REF and CK48 clock outputs
One 66.67MHz clock input, used to develop the CK66 and PCI clock outputs
Two 48MHz clock outputs
Six 66MHz clock outputs, developed as buffered copies of the 66REF reference input
Twelve 33.33MHz PCI clock outputs, developed as a divide-by-two of the 66REF reference
input. Groups of PCI outputs can be disabled via SEL_Q, SEL_R, and SEL_S (see Table 4).
Individual outputs can be disabled via the serial interface.
Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state.
Two 3.3V REF clock outputs, developed as buffered copies of the 14REF reference input
SMBus serial interface clock input
SMBus serial interface data input/output
Three clock management select inputs, used to enable, disable, or tristate groups of clock
outputs
3.3V ± 5% power supply for PLL core
3.3V power supply for CK48 clock outputs
3.3V power supply for CK66 clock outputs
3.3V power supply for the 14REF and the 66REF reference inputs
3.3V power supply for the PCI clock outputs
3.3V power supply for the REF clock outputs
3.3V power supply for the serial interface and digital input pins
Ground for the PLL core
Ground for the CK48 clock outputs
Ground for the CK66 clock outputs
Ground for the 14REF and the 66REF reference inputs
Ground for the PCI clock outputs
Ground for REF clock outputs
Ground for the serial interface and digital input pins
SUPPLY
VDD_N
VDD_N
VDD_48
VDD_66
VDD_P
DI
DO
DI
DIO
DI
P
P
P
P
P
P
P
P
P
P
P
P
P
P
PWR_DWN#
REF_0:1
SCL
SDA
SEL_Q
SEL_R
SEL_S
VDD
VDD_48
VDD_66
VDD_N
VDD_P
VDD_R
VDD_S
VSS
VSS_48
VSS_66
VSS_N
VSS_P
VSS_R
VSS_S
VDD_S
VDD_R
VDD_S
VDD_S
VDD_S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ISO9001
2.27.02
2
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer IC
2.0
Programming Information
Table 4: Clock Enable Configuration
CONTROL INPUTS
(1)
PWR_DWN#
SEL_Q
SEL_R
SEL_S
CK48_0
CK48_1
CK66_0:4
CLOCK OUTPUTS (MHz)
CK66_5
REF_0:1
PCI_0:5
PCI_6:7
PCI_8:11
1
1
1
1
1
1
1
1
0
1.
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
48.008
48.008
48.008
48.008
tristate
48.008
48.008
48.008
stopped
low
48.008
48.008
48.008
48.008
tristate
48.008
48.008
stopped
low
stopped
low
66.67
66.67
66.67
66.67
tristate
66.67
66.67
66.67
stopped
low
66.67
66.67
66.67
66.67
tristate
stopped
low
66.67
66.67
stopped
low
14.318
14.318
14.318
14.318
tristate
14.318
stopped
low
14.318
stopped
low
33.33
stopped
low
stopped
low
stopped
low
tristate
33.33
33.33
33.33
stopped
low
33.33
stopped
low
33.33
stopped
low
tristate
33.33
33.33
33.33
stopped
low
33.33
33.33
33.33
stopped
low
tristate
33.33
33.33
33.33
stopped
low
Control inputs override any SMBus register settings in situations where the outputs are stopped low
Table 5: Synthesis Offset
CLOCK
CK48
(1)
1.
3.0
DEVIATION
(ppm)
+167
Programming Interface
TARGET
(MHz)
48.00
ACTUAL
(MHz)
48.0080
This device supports the SMBus Block Write and Block
Read commands. The device address is as follows:
48MHz USB clock is required to be 167ppm off from 48.000MHz to conform to USB
requirements.
Table 6: Device Address
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
3.1
Block Write
The Block Write command allows the bus host to write
several bytes of data to sequential registers, starting with
the Byte 0 Register. As shown in Figure 2, a Block Write
starts with the seven-bit device address followed by a
logic-low R/W bit. After an acknowledge of the device
address and R/W bit by this device, a command code is
containing all zeroes (0000 0000) is written.
After the zero command code and an acknowledge, the
bus host then issues a byte count that describes the
number of data bytes to be written. The byte count must
be a minimum of one byte and a maximum of 32 bytes.
ISO9001
2.27.02
3
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer IC
Table 7: Byte Count
BYTE COUNT
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
to
0001 1111
0010 0000
DESCRIPTION
Not allowed: Must have at least one byte
Writes one byte (Byte 0)
Writes two bytes (Byte 0, 1 in order)
Writes three bytes (Byte 0, 1, 2 in order)
Writes four bytes (Byte 0, 1, 2, 3 in order)
Writes five bytes (Byte 0, 1, 2, 3, 4 in order)
These byte counts are ignored by this device
Maximum byte count supported (32)
3.2
Block Read
After an acknowledge of the byte count, data bytes may
be written starting with Register 0 and incrementing se-
quentially. An acknowledge by this device between each
byte of data must occur before the next data byte is sent.
The Block Read command, shown in Figure 3, permits
the host to read several bytes of data from sequential
registers, starting by default at Register 0. To perform a
Block Read procedure, the seven-bit device address is
sent, followed by a logic-high R/W bit.
Following an acknowledgement of the byte count by the
bus host, this device will take command of the bus and
will transmit all the data beginning with Register 0. After
the last byte of data, the host does not acknowledge the
final transfer but instead generates a STOP command. If
a NO-acknowledge does not occur, the device releases
the bus and the bus host will read all ones.
If the host does not want to receive all the data, the host
should not acknowledge the last data byte and instead
issue a STOP command on the next clock.
Figure 2: Block Write
S
DEVICE ADDRESS
W A
A
BYTE COUNT = N
A
DATA BYTE 1
A
DATA BYTE N
A P
7-bit Receive
Device Address
START
Command
Command Code
Acknowledge
WRITE Command
From bus host
to device
Byte Count
Data
Acknowledge
Acknowledge
Data
Acknowledge
STOP Command
Acknowledge
From device
to bus host
Figure 3: Block Read
S
DEVICE ADDRESS
R A
BYTE COUNT = N
A
DATA BYTE 1
A
DATA BYTE N
A P
7-bit Receive
Device Address
Repeat START
Byte Count
Acknowledge
READ Command
From bus host
to device
Data
Acknowledge
Acknowledge
From device
to bus host
Data
NO Acknowledge
STOP Command
ISO9001
2.27.02
4
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer IC
3.3
Register Programming
Table 10: Byte 2 Register
BIT
7
6
5
4
3
2
1
0
CLOCK
CK66_0
CK66_1
CK66_2
CK66_3
CK66_4
CK66_5
(reserved)
(reserved)
PIN
42
43
46
47
50
51
-
-
DESCRIPTION
1 = enabled, 0 = disabled
1 = enabled, 0 = disabled
1 = enabled, 0 = disabled
1 = enabled, 0 = disabled
1 = enabled, 0 = disabled
1 = enabled, 0 = disabled
Initialize to 0
Initialize to 0
A logic-one written to a valid bit location enables (turns
on) the assigned output clock. Likewise, a logic-zero
written to a valid bit location disables (turns off) the as-
signed output clock.
Any unused or reserved register bits should be cleared to
zero. These registers are expected to be configured at
power-up and are not expected to change during normal
modes of operation. Serial bits are read by this device
starting with Byte 0 and proceeding to Byte 4. Bit 7 of
each byte is read first, and bits are read in descending
order down to Bit 0.
Note that the SEL_Q, SEL_R and SEL_S pins will over-
ride any register settings when disabling outputs. Regis-
ter settings will only affect enabled outputs.
Upon application of VDD to the device, all register bits
are set to one (1) so that all outputs are enabled and ac-
tive. All programmed settings will be retained if the device
is powered-down via PWR_DWN# low. After powering-up
the device via PWR_DWN# the device will operate ac-
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