PRELIMINARY
CYUSB3014
EZ-USB
®
FX3 SuperSpeed USB Controller
Features
■
■
Ultra low-power in core power-down mode
❐
Less than 60 µA with VBATT ON and 20 µA with VBATT off
Independent power domains for core and I/O
❐
Core operation at 1.2 V
2
❐
I S, UART and SPI operation at 1.8 to 3.3V
2
❐
I C operation at 1.2 V
10 × 10 mm, 0.8 mm pitch Pb-free ball grid array (BGA) package
EZ USB
®
software and DVK for easy code development
Universal serial bus (USB) integration
❐
USB 3.0 and USB 2.0 peripheral compliant with USB3.0
specification 1.0
❐
5-Gbps USB3.0 PHY compliant with PIPE 3.0
❐
High-speed On-The-Go (HS-OTG) host and peripheral
compliant with On-The-Go Supplement Version 2.0
❐
Thirty-two physical endpoints
❐
Support for battery charging Spec 1.1 and accessory charger
adaptor (ACA) detection
General programmable interface (GPIF™ II)
❐
Programmable 100-MHz GPIF II interface enables
connectivity to wide range of external devices
❐
8-/16-/32-bit data bus
❐
Up to 16 configurable control signals
Fully accessible 32-bit CPU
❐
ARM926EJ Core with 200MHz operation
❐
512 kB Embedded SRAM
Additional connectivity to following peripherals
2
❐
I C master controller at 1 MHz
2
❐
I S master (transmitter only) at sampling frequencies 32 kHz,
44.1 kHz, 48 kHz
❐
UART support up to 4 Mbps
❐
SPI master at 33 MHz
Selectable clock input frequencies
❐
19.2, 26, 38.4, and 52 MHz
❐
19.2 MHz crystal input support
TRST#
TMS
TCK
TDI
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Applications
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Digital video camcorders
Digital still cameras
Printers
Scanners
Video capture cards
Test and measurement equipment
Surveillance cameras
Personal navigation devices
Medical imaging devices
Video IP phones
Portable media players
Industrial cameras
■
■
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FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
ARM926EJ -S
Embedded
SRAm
(512kB)
JTAG
TDO
Logic Block Diagram
HS/FS/LS
OTG Host
DATA[31:0
]
USB INTERFACE
CTL[12:0]
PMODE[2:0
]
GPIF™ II
32
EPs
HS/FS
Peripheral
INT#
RESET #
EZ-Dtect™
UART
SPI
I2S
SS
Peripheral
OTG_ID
SSRX -
SSRX +
SSTX -
SSTX +
D+
D-
I2C
I2C_SCL
TX
I2C_SDA
RX
CTS
RTS
SSN
SCK
I2S_CLK
I2S_WS
I2S_MSCLK
MOSI
MISO
I2S_SD
Cypress Semiconductor Corporation
Document Number 001-52136 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
• 408-943-2600
Revised July 7, 2011
PRELIMINARY
CYUSB3014
Contents
Functional Overview .......................................................... 3
Application Examples .................................................... 3
USB Interface ...................................................................... 4
OTG............................................................................... 4
ReNumeration ............................................................... 5
EZ-Dtect ........................................................................ 5
VBUS Overvoltage Protection ....................................... 5
Carkit UART Mode ........................................................ 5
GPIF II .................................................................................. 6
CPU ...................................................................................... 6
JTAG Interface .................................................................... 7
Other Interfaces .................................................................. 7
UART Interface.............................................................. 7
I2C Interface.................................................................. 7
I2S Interface .................................................................. 7
SPI Interface.................................................................. 7
Boot Options....................................................................... 7
Reset.................................................................................... 8
Hard Reset .................................................................... 8
Soft Reset...................................................................... 8
Clocking .............................................................................. 8
32-kHz Watchdog Timer Clock Input............................. 8
Power................................................................................... 9
Power Modes ................................................................ 9
Configuration Options ..................................................... 13
Digital I/Os.........................................................................
GPIOs.................................................................................
System Level ESD ............................................................
Absolute Maximum Ratings ............................................
Operating Conditions.......................................................
AC Timing Parameters .....................................................
GPIF II Timing .............................................................
Slave FIFO Interface ...................................................
Serial Peripherals Timing ............................................
Reset Sequence................................................................
Pin Description .................................................................
Package Diagram..............................................................
Ordering Information .......................................................
Ordering Code Definition.............................................
Acronyms ..........................................................................
Document Conventions ...................................................
Units of Measure .........................................................
Document History Page ...................................................
Sales, Solutions, and Legal Information ........................
Worldwide Sales and Design Support.........................
Products ......................................................................
PSoC Solutions ...........................................................
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Document Number 001-52136 Rev. *I
Page 2 of 38
PRELIMINARY
CYUSB3014
Functional Overview
Cypress EZ-USB FX3 is the next generation USB3.0 peripheral
controller providing highly integrated and flexible features that
enable developers to add USB3.0 functionality to any system.
EZ-USB FX3 has a fully configurable, parallel, General
Programmable Interface called GPIF II, which can connect to
any processor, ASIC, or FPGA. The General Programmable
Interface GPIF II is an enhanced version of the GPIF in FX2LP,
Cypress’s flagship USB2.0 product. It provides easy and
glueless connectivity to popular interfaces such as
asynchronous SRAM, asynchronous and synchronous Address
Data Multiplexed interface, parallel ATA, and so on.
EZ-USB FX3 has integrated USB3.0 and USB2.0 physical layer
(PHYs) along with a 32-bit ARM926EJ-S microprocessor for
powerful data processing and for building custom applications. It
implements an ingenious architecture which enables data
transfers of 320 MBps
[1]
from GPIF II to USB interface.
An integrated USB2.0 OTG controller enables applications that
need dual role usage scenarios, for example EZ-USB FX3 may
function as OTG Host to MSC and HID class devices.
EZ-USB FX3 contains 512 kB of on-chip SRAM for code and
data. EZ-USB FX3 also provides interfaces to connect to serial
peripherals such as UART, SPI, I
2
C, and I
2
S.
EZ-USB FX3 comes with the easy to use EZ-USB tools providing
a complete solution for fast application development. The
software development kit comes with application examples for
accelerating time to market.
EZ-USB FX3 is fully compliant to USB3.0 v1.0 specification and
is also backward compatible with USB2.0. It is also complaint
with the Battery Charging Specification v1.1 and USB2.0 OTG
Specification v2.0.
Application Examples
Figure 1
and
Figure 2
show typical application diagrams for
EZ-USB FX3.
Figure 1
shows a typical application diagram in
which EZ-USB FX3 functions as a co-processor and connects to
an external processor responsible for various system level
functions.
Figure 2
shows a typical application diagram when
EZ-USB FX3 functions as the main processor in the system.
Figure 1. EZ-USB FX3 as a Co-processor
CRYSTAL*
POWER
SUBSYSTEM
External Processor
text
(example: MCU/CPU/ASIC/
FPGA)
GPIF II
EZ-USB FX3
(ARM9 Core)
USB
Port
USB Host
XTALOUT
Serial Interfaces
(example: I2C)
External Serial Peripheral
(example: EEPROM)
* A clock input may be provided on the
CLKIN pin instead of a crystal input
Note
1. Assuming that GPIF II is configured for 32 bit data bus synchronous interface operating at 100 MHz. This number also includes protocol overheads.
Document Number 001-52136 Rev. *I
XTALIN
Page 3 of 38
PRELIMINARY
CYUSB3014
Figure 2. EZ-USB FX3 as Main Processor
CRYSTAL*
XTALOUT
EXTERNAL SLAVE
DEVICE
(Eg: IMAGE SENSOR)
GPIF II
EZ-USB FX3
(ARM9 Core)
XTALIN
USB
Port
USB Host
I2C
* A clock input may be provided on the
CLKIN pin instead of a crystal input
EEPROM
USB Interface
EZ-USB FX3 supports USB peripheral functionality compliant
with USB 3.0 Specification Revision 1.0 and is also backward
compatible with the USB 2.0 Specification.
EZ-USB FX3 is compliant with On-The-Go Supplement Revision
2.0. It supports Hi-Speed, Full-Speed, and Low Speed OTG dual
role device capability. It is SuperSpeed, High-Speed, and
Full-Speed capable as a peripheral and High-Speed, Full-Speed,
and Low-Speed capable as a host.
EZ-USB FX3 supports Carkit Pass-Through UART functionality
on USB D+/D- lines based on the CEA-936A specification.
EZ-USB FX3 supports up to 16 IN and 16 OUT endpoints.
EZ-USB FX3 fully supports the USB3.0 Streams feature. It also
supports USB Attached SCSI (UAS) device class to optimize
mass storage access performance.
As a USB peripheral, EZ-USB FX3 supports UAS, USB Video
Class (UVC), Mass Storage Class (MSC), and Media Transfer
Protocol (MTP) USB peripheral classes. As a USB peripheral, all
other device classes are supported only in pass through mode
when handled entirely by a host processor external to the device.
As an OTG host, EZ-USB FX3 supports MSC and HID device
classes.
When the USB port is not in use, the PHY and transceiver may
be disabled for power savings.
Figure 3. USB Interface Signals
EZ-USB FX3
VBATT
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
OTG
EZ-USB FX3 is compliant with the On-The-Go (OTG) Specifi-
cation Revision 2.0 .
In OTG mode, EZ-USB FX3 supports both A and B device mode
and supports Control, Interrupt, Bulk, and Isochronous data
transfers.
EZ-USB FX3 requires an external charge pump (either stand
alone or integrated into a PMIC) to power VBUS in OTG A-device
mode.
The Target Peripheral List for OTG host implementation consists
of MSC and HID class devices.
Attach Detection Protocol (ADP) is not supported by EZ-USB
FX3.
Document Number 001-52136 Rev. *I
USB Interface
Page 4 of 38
PRELIMINARY
CYUSB3014
OTG Connectivity
In OTG mode, EZ-USB FX3 can be configured to be A, B, or dual
role device. It is able to connect to:
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VBUS Overvoltage Protection
The maximum input voltage on EZ-USB FX3's VBUS pin is 6V.
A charger can supply up to 9V on VBUS, in this case, it is
necessary to have an external Over voltage Protection (OVP)
device to protect EZ-USB FX3 from damage on VBUS.
Figure 4
shows the system application diagram with an OVP device
connected on VBUS. Please refer to
Table 7DC
Specifications
for the operating range of VBUS and VBATT.
ACA device
Targeted USB peripheral
SRP capable USB peripheral
HNP capable USB peripheral
OTG host
HNP capable host
OTG device
Figure 4. System Diagram with OVP Device For VBUS
POWER SUBSYSTEM
U3RXVDDQ
U3TXVDDQ
CVDDQ
VIO5
Because EZ-USB FX3's configuration is soft, one chip can take
on the identities of multiple distinct USB devices.
When first plugged into USB, EZ-USB FX3 enumerates
automatically with the Cypress Vendor ID (0x04B4) and
downloads firmware and USB descriptors over the USB
interface. The downloaded firmware executes a electrical
disconnect and connect. EZ-USB FX3 enumerates again, this
time as a device defined by the downloaded information. This
patented two step process called ReNumeration happens
instantly when the device is plugged in.
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
GND
EZ-USB FX3
1
2
USB Connector
3
4
5
6
7
8
9
OVP device
EZ-Dtect
EZ-USB FX3 supports USB Charger and accessory detection
(EZ-Dtect). The charger detection mechanism is in compliance
with the Battery Charging Specification Revision 1.1. In addition
to supporting this version of the specification EZ-USB FX3 also
provides hardware support to detect the resistance values on the
ID pin.
The following are the resistance ranges that EZ-USB FX3 can
detect:
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Carkit UART Mode
The USB interface supports Carkit UART mode (UART over
D+/D-) for non-USB serial data transfer. This is based on the
CEA-936A specification.
In Carkit UART mode, the output signaling voltage is 3.3V. When
configured for Carkit UART mode, TXD of UART (output) is
mapped to D- line, and RXD of UART (input) is mapped to D+
line.
In Carkit mode, EZ-USB FX3 disables the USB transceiver and
D+ and D- pins serve as pass through pins to connect to the
UART of the host processor. The Carkit UART signals may be
routed to the GPIF II interface or to GPIO[48] and GPIO[49] as
shown in
Figure 5
on page 6.
A rate of up to 9600 bps is supported by EZ-USB FX3 in this
mode.
Less than 10
Less than 1 k
65 k to 72 k
35 kto 39 k
99.96 k to 104.4 k (102 k2%)
119 k to 132 k
Higher than 220 k
431.2 k to 448.8 k (440 k2%)
EZ-USB FX3's charger detection feature detects a dedicated
wall charger, Host/Hub charger, and Host/Hub.
Document Number 001-52136 Rev. *I
USB-Port
Page 5 of 38
AVDD
VDD
VIO2
VIO1
VIO3
VIO4
ReNumeration
传感器
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