CYRF6936
WirelessUSB™ LP 2.4 GHz Radio SoC
Features
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Battery Voltage Monitoring Circuitry
Supports coin-cell operated applications
Operating voltage from 1.8 V to 3.6 V
Operating temperature from 0 to 70°C
Space saving 40-pin QFN 6x6 mm package
2.4 GHz Direct Sequence Spread Spectrum (DSSS) radio
transceiver
Operates in the unlicensed worldwide Industrial, Scientific,
and Medical (ISM) band (2.400 GHz to 2.483 GHz)
21 mA operating current (Transmit at –5 dBm)
Transmit power up to +4 dBm
Receive sensitivity up to –97 dBm
Sleep Current less than 1
μA
DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps
Low external component count
Auto Transaction Sequencer (ATS) - no MCU intervention
Framing, Length, CRC16, and Auto ACK
Power Management Unit (PMU) for MCU/Sensor
Fast Startup and Fast Channel Changes
Separate 16-byte Transmit and Receive FIFOs
AutoRate™ - dynamic data rate reception
Receive Signal Strength Indication (RSSI)
Serial Peripheral Interface (SPI) control while in sleep mode
4 MHz SPI microcontroller interface
Applications
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Wireless Keyboards and Mice
Wireless Gamepads
Remote Controls
Toys
VOIP and Wireless Headsets
White Goods
Consumer Electronics
Home Automation
Automatic Meter Readers
Personal Health and Entertainment
Applications Support
See
www.cypress.com
for development tools, reference
designs, and application notes.
Logic Block Diagram
V
BAT
L/D
V
REG
V
DD
V
CC
PACTL
Power Management
Data
Interface
and
Sequencer
DSSS
Baseband
& Framer
GFSK
Modulator
RF
P
RF
N
RF
BIAS
IRQ
SS
SCK
MISO
MOSI
SPI
RSSI
Xtal Osc
RST
XTAL XOUT
GND
GFSK
Demodulator
Synthesizer
Cypress Semiconductor Corporation
Document #: 38-16015 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 18, 2011
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CYRF6936
Contents
Functional Description ..................................................... 3
Functional Overview ........................................................ 4
Data Transmission Modes ........................................... 4
Link Layer Modes ........................................................ 4
Packet Buffers ............................................................. 5
Auto Transaction Sequencer (ATS) ............................ 5
Data Rates .................................................................. 6
Functional Block Overview .............................................. 6
2.4 GHz Radio ............................................................. 6
Frequency Synthesizer ................................................ 6
Baseband and Framer ................................................. 6
Packet Buffers and Radio Configuration Registers ..... 6
SPI Interface ................................................................ 6
Interrupts ..................................................................... 8
Clocks .......................................................................... 8
Power Management .................................................... 8
Low Noise Amplifier and Received
Signal Strength Indication ............................................ 8
Receive Spurious Response ....................................... 9
Application Examples ......................................................9
Registers .........................................................................14
Absolute Maximum Ratings ...........................................15
Operating Conditions .....................................................15
DC Characteristics ..........................................................15
AC Characteristics ..........................................................16
RF Characteristics ..........................................................17
Typical Operating Characteristics .................................19
Ordering Information ......................................................22
Ordering Code Definitions .........................................22
Package Description ......................................................23
Acronyms ........................................................................25
Document Conventions .................................................25
Units of Measure .......................................................25
Document History Page .................................................26
Sales, Solutions, and Legal Information ......................28
Worldwide Sales and Design Support .......................28
Products ....................................................................28
PSoC Solutions .........................................................28
Document #: 38-16015 Rev. *J
Page 2 of 28
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CYRF6936
Functional Description
The CYRF6936 WirelessUSB™ LP radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip
(SoC) family. The CYRF6936 is interoperable with the first generation CYWUSB69xx devices. The CYRF6936 IC adds a range
of enhanced features, including increased operating voltage range, reduced supply current in all operating modes, higher data
rate options, reduced crystal start up, synthesizer settling, and link turnaround times.
Figure 1. Pin Diagram - CYRF6936 40 QFN
V
BAT0
38
V
REG
40
RST 34
V
DD
35
L/D 37
V
I/O
33
NC 39
NC 36
NC 31
NC 32
Corner
tabs
XTAL
NC
V
CC
NC
NC
V
BAT1
V
CC
V
BAT2
NC
1
2
3
4
5
6
7
8
9
* E-PAD Bottom Side
30 PACTL / GPIO
29 XOUT / GPIO
28 MISO / GPIO
CYRF6936
WirelessUSB LP
40-Pin QFN
27 MOSI / SDAT
26 IRQ / GPIO
25 SCK
24 SS
23 NC
22 NC
21 NC
RF
BIAS
10
11 RF
P
12 GND
13 RF
N
14 NC
15 NC
16 V
CC
17 NC
18 NC
19 RESV
20 NC
Table 1. Pin Description
Pin Number
1
Name
XTAL
Type
I
NC
Default
I
12 MHz crystal.
Connect to GND.
Description
2, 4, 5, 9, 14, 15, 17, 18, NC
20, 21, 22, 23, 31, 32,
36, 39
3, 7, 16
6, 8, 38
10
11
12
13
19
24
25
26
27
28
29
30
33
V
CC
V
BAT(0-2)
RF
BIAS
RF
P
GND
RF
N
RESV
SS
SCK
IRQ
MOSI
MISO
XOUT
PACTL
V
I/O
Pwr
Pwr
O
I/O
GND
I/O
I
I
I
I/O
I/O
I/O
I/O
I/O
Pwr
I
I
O
I
Z
O
O
I
O
I
V
CC
= 2.4 V to 3.6 V. Typically connected to V
REG.
V
BAT
= 1.8 V to 3.6 V. Main supply.
RF I/O 1.8 V reference voltage.
Differential RF signal to and from antenna.
Ground.
Differential RF signal to and from antenna.
Must be connected to GND.
SPI enable, active LOW assertion. Enables and frames transfers.
SPI clock.
Interrupt output (configurable active HIGH or LOW), or GPIO.
SPI data input pin (Master Out Slave In), or SDAT.
SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tri-states when SPI 3PIN = 0 and SS is deasserted.
Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.
Tri-states in sleep mode (configure as GPIO drive LOW).
Control signal for external PA, T/R switch, or GPIO.
I/O interface voltage, 1.8–3.6 V.
Document #: 38-16015 Rev. *J
Page 3 of 28
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CYRF6936
Table 1. Pin Description
(continued)
Pin Number
34
Name
RST
Type
I
Default
I
Description
Device reset. Internal 10 kohm pull down resistor. Active HIGH,
connect through a 0.47
μF
capacitor to V
BAT.
Must have RST = 1 event
the first time power is applied to the radio. Otherwise the state of the
radio control registers is unknown.
Decoupling pin for 1.8 V logic regulator, connect through a 0.47
μF
capacitor to GND.
PMU inductor/diode connection, when used. If not used, connect to
GND.
PMU boosted output voltage feedback.
Must be soldered to Ground.
Do Not solder the tabs and keep other signal traces clear. All tabs are
common to the lead frame or paddle which is grounded after the pad
is grounded. While they are visible to the user, they do not extend to
the bottom.
35
37
40
E-PAD
Corner Tabs
V
DD
L/D
V
REG
GND
NC
Pwr
O
Pwr
GND
NC
Functional Overview
The CYRF6936 IC provides a complete WirelessUSB SPI to
antenna wireless MODEMs. The SoC is designed to implement
wireless device links operating in the worldwide 2.4 GHz ISM
frequency band. It is intended for systems compliant with
worldwide regulations covered by ETSI EN 301 489-1 V1.41,
ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA
and Industry Canada), and TELEC ARIB_T66_March, 2003
(Japan).
The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband controller,
Received Signal Strength Indication (RSSI), and SPI interface
for data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
The baseband performs DSSS spreading/despreading, Start of
Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be configured
to automatically transmit Acknowledge (ACK) handshake
packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
In addition, the CYRF6936 IC has a Power Management Unit
(PMU), which enables direct connection of the device to any
battery voltage in the range 1.8 V to 3.6 V. The PMU conditions
the battery voltage to provide the supply voltages required by the
device, and may supply external devices.
Data Transmission Modes
The SoC supports four different data transmission modes:
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In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
In 8DR mode, eight bits are encoded in each derived code
symbol transmitted.
In DDR mode, two bits are encoded in each derived code
symbol transmitted (As in the CYWUSB6934 DDR mode).
In SDR mode, one bit is encoded in each derived code symbol
transmitted (As in the CYWUSB6934 standard modes).
Both 64 chip and 32 chip Pseudo Noise (PN) codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
sent in the same mode. In general, lower data rates reduce
packet error rate in any given environment.
Link Layer Modes
The CYRF6936 IC device supports the following data packet
framing features:
SOP
Packets begin with a two-symbol SoP marker. This is required in
GFSK and 8DR modes, but is optional in DDR mode and is not
supported in SDR mode. If framing is disabled then an SOP
event is inferred whenever two successive correlations are
detected. The SOP_CODE_ADR code used for the SOP is
different from that used for the “body” of the packet, and if desired
may be a different length. SOP must be configured to be the
same length on both sides of the link.
Length
There are two options for detecting the end of a packet. If SOP
is enabled, then the length field must be enabled. GFSK and
8DR must enable the length field. This is the first eight bits after
the SOP symbol, and is transmitted at the payload data rate.
When the length field is enabled, an EoP condition is inferred
after reception of the number of bytes defined in the length field,
plus two bytes for the CRC16. The alternative to using the length
Page 4 of 28
Document #: 38-16015 Rev. *J
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CYRF6936
field is to infer an EOP condition from a configurable number of
successive noncorrelations; this option is not available in GFSK
mode and is only recommended when using SDR mode.
CRC16
The device may be configured to append a 16 bit CRC16 to each
packet. The CRC16 uses the USB CRC polynomial with the
added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The seed value for the CRC16
calculation is configurable, and the CRC16 transmitted may be
calculated using either the loaded seed value or a zero seed; the
received data CRC16 is checked against both the configured
and zero CRC16 seeds.
CRC16 detects the following errors:
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Any one bit in error.
Any two bits in error (irrespective of how far apart, which
column, and so on).
Any odd number of bits in error (irrespective of the location).
An error burst as wide as the checksum itself.
Figure 2
shows an example packet with SOP, CRC16, and
lengths fields enabled, and
Figure 3
shows a standard ACK
packet.
Figure 2. Example Packet Format
P re a m b le
n x 16us
2 n d F ra m in g
S y m b o l*
P
SOP 1
1 s t F ra m in g
S y m b o l*
SOP 2
L e n g th
Packet
le n g th
1 B y te
P e rio d
P a y lo a d D a ta
C R C 16
*N o te :3 2 o r 6 4 u s
Figure 3. Example ACK Packet Format
P r e a m b le
n x 16us
2 n d F r a m in g
S y m b o l*
P
SO P 1
1 s t F r a m in g
S y m b o l*
SO P 2
C RC 16
C R C fie ld fr o m
r e c e iv e d p a c k e t.
2 B y te p e r io d s
*N o te :3 2 o r 6 4 u s
Packet Buffers
All data transmission and reception use the 16 byte packet
buffers - one for transmission and one for reception.
The transmit buffer allows loading a complete packet of up to 16
bytes of payload data in one burst SPI transaction. This is then
transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.
The CYRF6936 IC supports packets up to 255 bytes. However,
the actual maximum packet length depends on the accuracy of
the clock on each end of the link and the data mode. Interrupts
are provided to allow an MCU to use the transmit and receive
buffers as FIFOs. When transmitting a packet longer than 16
bytes, the MCU can load 16 bytes initially, and add further bytes
to the transmit buffer as transmission of data creates space in
the buffer. Similarly, when receiving packets longer than 16
bytes, the MCU must fetch received data from the FIFO
periodically during packet reception to prevent it from
overflowing.
Auto Transaction Sequencer (ATS)
The CYRF6936 IC provides automated support for transmission
and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
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starts the crystal and synthesizer
enters transmit mode
transmits the packet in the transmit buffer
transitions to receive mode and waits for an ACK packet
transitions to the transaction end state when an ACK packet is
received or a timeout period expires
Similarly, when receiving in transaction mode, the device
automatically:
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waits in receive mode for a valid packet to be received
transitions to transmit mode, transmits an ACK packet
transitions to the transaction end state (receive mode to await
the next packet, and so on.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
Document #: 38-16015 Rev. *J
Page 5 of 28
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